Altium

Design Rule Verification Report

Date	:	7/16/2014
Time	:	1:05:02 PM
Elapsed Time	:	00:00:00
Filename	:	D:\Dropbox\altium\mit\rf_amp\pwr_block.PcbDoc

Warnings	:	0
Rule Violations	:	2

Summary

Warnings	Count
Total	0

Rule Violations	Count
Net Antennae (Tolerance=0mil) (All)	0
Silk primitive without silk layer	2
Silk to Silk (Clearance=10mil) (Disabled)(All),(All)	0
Silk To Solder Mask (Clearance=10mil) (Disabled)(IsPad),(All)	0
Minimum Solder Mask Sliver (Gap=10mil) (Disabled)(All),(All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Hole Size Constraint (Min=12mil) (Max=100mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Width Constraint (Min=12mil) (Max=60mil) (Preferred=60mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Clearance Constraint (Gap=10mil) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Total	2

Silk primitive without silk layer
Silk To Board Region Clearance (Out of silkscreen region) : Track (2632.48mil,977.559mil)(2632.48mil,1922.441mil) Top Overlay
Silk To Board Region Clearance (Out of silkscreen region) : Text "RF_NFET" (2116.5mil,882.5mil) Top Overlay