Design Rule Verification Report

Date:		5/27/2018
Time:		12:28:15 AM
Elapsed Time:		00:00:01
Filename:		C:\Users\Public\Documents\Altium\Projects\VestibulatorMotor\PCB1.PcbDoc

Warnings:		3
Rule Violations:		60

Summary

Warnings	Count
Zero hole size multi-layer pad(s) detected	3
Total	3

Rule Violations	Count
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Clearance Constraint (Gap=6mil) (All),(All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=16mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Hole Size Constraint (Min=1mil) (Max=100mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All)	22
Silk To Solder Mask (Clearance=10mil) (IsPad),(All)	36
Silk to Silk (Clearance=10mil) (All),(All)	2
Net Antennae (Tolerance=0mil) (All)	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Total	60

Warnings

Zero hole size multi-layer pad(s) detected
Pad J?-2(1220.047mil,955.33mil) on Multi-Layer on Net NetJ?_2
Pad J?-1(1220.047mil,903.21mil) on Multi-Layer on Net GND
Pad J?-3(1220.047mil,1007.451mil) on Multi-Layer on Net VCC

Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-9(1460.63mil,1246.063mil) on Top Layer And Pad U1-8(1460.63mil,1220.472mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-10(1460.63mil,1271.653mil) on Top Layer And Pad U1-9(1460.63mil,1246.063mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-11(1460.63mil,1297.244mil) on Top Layer And Pad U1-10(1460.63mil,1271.653mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-12(1460.63mil,1322.835mil) on Top Layer And Pad U1-11(1460.63mil,1297.244mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-13(1460.63mil,1348.425mil) on Top Layer And Pad U1-12(1460.63mil,1322.835mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-14(1460.63mil,1374.016mil) on Top Layer And Pad U1-13(1460.63mil,1348.425mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-6(1240.158mil,1246.063mil) on Top Layer And Pad U1-7(1240.158mil,1220.472mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-5(1240.158mil,1271.653mil) on Top Layer And Pad U1-6(1240.158mil,1246.063mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-4(1240.158mil,1297.244mil) on Top Layer And Pad U1-5(1240.158mil,1271.653mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-3(1240.158mil,1322.835mil) on Top Layer And Pad U1-4(1240.158mil,1297.244mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-2(1240.158mil,1348.425mil) on Top Layer And Pad U1-3(1240.158mil,1322.835mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (1.843mil < 10mil) Between Pad U1-1(1240.158mil,1374.016mil) on Top Layer And Pad U1-2(1240.158mil,1348.425mil) on Top Layer [Top Solder] Mask Sliver [1.843mil]
Minimum Solder Mask Sliver Constraint: (2.827mil < 10mil) Between Pad U2-10(1350.433mil,1000.394mil) on Top Layer And Pad U2-1(1315mil,995.472mil) on Top Layer [Top Solder] Mask Sliver [2.827mil]
Minimum Solder Mask Sliver Constraint: (3.838mil < 10mil) Between Pad U2-10(1350.433mil,1000.394mil) on Top Layer And Pad U2-2(1315mil,975.787mil) on Top Layer [Top Solder] Mask Sliver [3.838mil]
Minimum Solder Mask Sliver Constraint: (4.587mil < 10mil) Between Pad U2-5(1350.433mil,929.528mil) on Top Layer And Pad U2-3(1315mil,956.102mil) on Top Layer [Top Solder] Mask Sliver [4.587mil]
Minimum Solder Mask Sliver Constraint: (2.827mil < 10mil) Between Pad U2-5(1350.433mil,929.528mil) on Top Layer And Pad U2-4(1315mil,936.417mil) on Top Layer [Top Solder] Mask Sliver [2.827mil]
Minimum Solder Mask Sliver Constraint: (2.827mil < 10mil) Between Pad U2-10(1350.433mil,1000.394mil) on Top Layer And Pad U2-9(1385.866mil,995.472mil) on Top Layer [Top Solder] Mask Sliver [2.827mil]
Minimum Solder Mask Sliver Constraint: (3.838mil < 10mil) Between Pad U2-10(1350.433mil,1000.394mil) on Top Layer And Pad U2-8(1385.866mil,975.787mil) on Top Layer [Top Solder] Mask Sliver [3.838mil]
Minimum Solder Mask Sliver Constraint: (4.587mil < 10mil) Between Pad U2-5(1350.433mil,929.528mil) on Top Layer And Pad U2-7(1385.866mil,956.102mil) on Top Layer [Top Solder] Mask Sliver [4.587mil]
Minimum Solder Mask Sliver Constraint: (2.827mil < 10mil) Between Pad U2-5(1350.433mil,929.528mil) on Top Layer And Pad U2-6(1385.866mil,936.417mil) on Top Layer [Top Solder] Mask Sliver [2.827mil]
Minimum Solder Mask Sliver Constraint: (4.751mil < 10mil) Between Pad J?-3(1220.047mil,1007.451mil) on Multi-Layer And Pad J?-2(1220.047mil,955.33mil) on Multi-Layer [Top Solder] Mask Sliver [4.751mil]
Minimum Solder Mask Sliver Constraint: (4.751mil < 10mil) Between Pad J?-1(1220.047mil,903.21mil) on Multi-Layer And Pad J?-2(1220.047mil,955.33mil) on Multi-Layer [Top Solder] Mask Sliver [4.751mil]

Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (8.076mil < 10mil) Between Track (1489.722mil,1494.293mil)(1494.936mil,1494.293mil) on Top Overlay And Pad C2-1(1464.449mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.076mil]
Silk To Solder Mask Clearance Constraint: (7.563mil < 10mil) Between Track (1487.114mil,1494.293mil)(1489.722mil,1494.293mil) on Top Overlay And Pad C2-1(1464.449mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.563mil]
Silk To Solder Mask Clearance Constraint: (7.374mil < 10mil) Between Track (1487.297mil,1572.114mil)(1497.543mil,1572.114mil) on Top Overlay And Pad C2-1(1464.449mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.374mil]
Silk To Solder Mask Clearance Constraint: (7.504mil < 10mil) Between Track (1497.543mil,1494.293mil)(1497.543mil,1572.114mil) on Top Overlay And Pad C2-1(1464.449mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.504mil]
Silk To Solder Mask Clearance Constraint: (7.225mil < 10mil) Between Track (1370.77mil,1572.016mil)(1373.377mil,1572.016mil) on Top Overlay And Pad C2-2(1395.551mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.225mil]
Silk To Solder Mask Clearance Constraint: (7.643mil < 10mil) Between Track (1365.556mil,1572.016mil)(1370.77mil,1572.016mil) on Top Overlay And Pad C2-2(1395.551mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.643mil]
Silk To Solder Mask Clearance Constraint: (7.637mil < 10mil) Between Track (1362.948mil,1494.195mil)(1373.194mil,1494.195mil) on Top Overlay And Pad C2-2(1395.551mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.637mil]
Silk To Solder Mask Clearance Constraint: (9.988mil < 10mil) Between Track (1362.948mil,1572.016mil)(1365.556mil,1572.016mil) on Top Overlay And Pad C2-2(1395.551mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.988mil]
Silk To Solder Mask Clearance Constraint: (7.012mil < 10mil) Between Track (1362.948mil,1494.195mil)(1362.948mil,1572.016mil) on Top Overlay And Pad C2-2(1395.551mil,1533.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.012mil]
Silk To Solder Mask Clearance Constraint: (8.469mil < 10mil) Between Track (1435.102mil,1001.968mil)(1435.102mil,1019.21mil) on Top Overlay And Pad C3-2(1464.567mil,993.118mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.469mil]
Silk To Solder Mask Clearance Constraint: (8.857mil < 10mil) Between Track (1494.42mil,1002.584mil)(1494.42mil,1019.21mil) on Top Overlay And Pad C3-2(1464.567mil,993.118mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.857mil]
Silk To Solder Mask Clearance Constraint: (8.343mil < 10mil) Between Track (1435.102mil,1019.21mil)(1494.42mil,1019.21mil) on Top Overlay And Pad C3-2(1464.567mil,993.118mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.343mil]
Silk To Solder Mask Clearance Constraint: (8.469mil < 10mil) Between Track (1435.102mil,904.063mil)(1435.102mil,920.688mil) on Top Overlay And Pad C3-1(1464.567mil,930.118mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.469mil]
Silk To Solder Mask Clearance Constraint: (8.857mil < 10mil) Between Track (1494.42mil,904.063mil)(1494.42mil,921.304mil) on Top Overlay And Pad C3-1(1464.567mil,930.118mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.857mil]
Silk To Solder Mask Clearance Constraint: (8.307mil < 10mil) Between Track (1435.102mil,904.063mil)(1494.42mil,904.063mil) on Top Overlay And Pad C3-1(1464.567mil,930.118mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.307mil]
Silk To Solder Mask Clearance Constraint: (9.598mil < 10mil) Between Text "+" (1358.003mil,1104.792mil) on Top Overlay And Pad LED1-1(1384.842mil,1113.189mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.598mil]
Silk To Solder Mask Clearance Constraint: (8.469mil < 10mil) Between Track (1374.491mil,1433.133mil)(1391.733mil,1433.133mil) on Top Overlay And Pad C1-2(1400.583mil,1462.598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.469mil]
Silk To Solder Mask Clearance Constraint: (8.857mil < 10mil) Between Track (1374.491mil,1492.451mil)(1391.117mil,1492.451mil) on Top Overlay And Pad C1-2(1400.583mil,1462.598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.857mil]
Silk To Solder Mask Clearance Constraint: (8.343mil < 10mil) Between Track (1374.491mil,1433.133mil)(1374.491mil,1492.451mil) on Top Overlay And Pad C1-2(1400.583mil,1462.598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.343mil]
Silk To Solder Mask Clearance Constraint: (8.469mil < 10mil) Between Track (1473.013mil,1433.133mil)(1489.638mil,1433.133mil) on Top Overlay And Pad C1-1(1463.583mil,1462.598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.469mil]
Silk To Solder Mask Clearance Constraint: (8.857mil < 10mil) Between Track (1472.397mil,1492.451mil)(1489.638mil,1492.451mil) on Top Overlay And Pad C1-1(1463.583mil,1462.598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.857mil]
Silk To Solder Mask Clearance Constraint: (8.307mil < 10mil) Between Track (1489.638mil,1433.133mil)(1489.638mil,1492.451mil) on Top Overlay And Pad C1-1(1463.583mil,1462.598mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.307mil]
Silk To Solder Mask Clearance Constraint: (7.179mil < 10mil) Between Track (1305.408mil,1084.03mil)(1318.187mil,1084.03mil) on Top Overlay And Pad R2-2(1292.331mil,1112.205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.179mil]
Silk To Solder Mask Clearance Constraint: (8.12mil < 10mil) Between Track (1305.621mil,1141.321mil)(1318.187mil,1141.321mil) on Top Overlay And Pad R2-2(1292.331mil,1112.205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.12mil]
Silk To Solder Mask Clearance Constraint: (8.108mil < 10mil) Between Track (1318.187mil,1084.03mil)(1318.187mil,1141.321mil) on Top Overlay And Pad R2-2(1292.331mil,1112.205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.108mil]
Silk To Solder Mask Clearance Constraint: (7.818mil < 10mil) Between Track (1204.031mil,1083.39mil)(1216.596mil,1083.39mil) on Top Overlay And Pad R2-1(1229.331mil,1112.205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.818mil]
Silk To Solder Mask Clearance Constraint: (7.481mil < 10mil) Between Track (1204.031mil,1140.682mil)(1216.809mil,1140.682mil) on Top Overlay And Pad R2-1(1229.331mil,1112.205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.481mil]
Silk To Solder Mask Clearance Constraint: (7.552mil < 10mil) Between Track (1204.031mil,1083.39mil)(1204.031mil,1140.682mil) on Top Overlay And Pad R2-1(1229.331mil,1112.205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.552mil]
Silk To Solder Mask Clearance Constraint: (6.062mil < 10mil) Between Text "Vestibulator Rev 0.2 Brett Smith 5/12/18" (1475mil,1550mil) on Bottom Overlay And Pad Free-6(1550mil,800mil) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [6.062mil]
Silk To Solder Mask Clearance Constraint: (8.587mil < 10mil) Between Text "C3" (1521mil,952mil) on Top Overlay And Pad H2-1(1600mil,1000mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [8.587mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "LATCH" (1556mil,990mil) on Bottom Overlay And Pad H2-1(1600mil,1000mil) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "CLK" (1556mil,1090mil) on Bottom Overlay And Pad H2-2(1600mil,1100mil) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "DIN" (1556mil,1190mil) on Bottom Overlay And Pad H2-3(1600mil,1200mil) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "CLR" (1556mil,1290mil) on Bottom Overlay And Pad H2-4(1600mil,1300mil) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "GND" (1556mil,1390mil) on Bottom Overlay And Pad H2-5(1600mil,1400mil) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "VCC" (1556mil,1490mil) on Bottom Overlay And Pad H2-6(1600mil,1500mil) on Multi-Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]

Silk to Silk (Clearance=10mil) (All),(All)
Silk To Silk Clearance Constraint: (8.609mil < 10mil) Between Text "C2" (1512.795mil,1523.622mil) on Top Overlay And Track (1497.543mil,1494.293mil)(1497.543mil,1572.114mil) on Top Overlay Silk Text to Silk Clearance [8.609mil]
Silk To Silk Clearance Constraint: (Collision < 10mil) Between Text "Vestibulator Rev 0.2 Brett Smith 5/12/18" (1475mil,1550mil) on Bottom Overlay And Text "LATCH" (1556mil,990mil) on Bottom Overlay Silk Text to Silk Clearance [0mil]