(kicad_pcb (version 20171130) (host pcbnew "(5.1.5)-3")
  (general
    (thickness 1.6)
    (drawings 5)
    (tracks 0)
    (zones 0)
    (modules 1)
    (nets 1)
  )
  (page A4)
  (title_block
    (title "16 mm Test Board")
    (rev 1.0)
    (company "Würth Elektronik")
    (comment 4 "Dakota Woertink")
  )
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (via_size 0.8)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 12.5 12.5)
    (pad_drill 0)
    (pad_to_mask_clearance 0.051)
    (solder_mask_min_width 0.25)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFFFF)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.8)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
  )
  (module 16_mm:16_mm (layer F.Cu) (tedit 664D0BC1)
    (at 140 88)
    (fp_text reference "16 mm" (at 11 -6) (layer F.SilkS))
    (fp_text value 16_mm (at -10 -6) (layer F.Fab))
    (pad 2 smd rect (at 0 33.75) (size 12.5 12.5) (layers F.Cu F.Paste F.Mask))
    (pad 1 thru_hole circle (at 0 0) (size 10 10) (drill 5) (layers *.Cu *.Mask))
  )
  (gr_line (start 160 128) (end 160 78) (layer Edge.Cuts) (width 0.12))
  (gr_line (start 120 128) (end 160 128) (layer Edge.Cuts) (width 0.12))
  (gr_line (start 120 78) (end 120 128) (layer Edge.Cuts) (width 0.12))
  (gr_line (start 160 78) (end 120 78) (layer Edge.Cuts) (width 0.12))
)
