Rev 1
DS3231 RTC
Designed by: MrSwirlyEyes
Rev 1
DS3231 RTC
Designed by: MrSwirlyEyes
CHIP, 1 X 0.5 X 0.55 mm body
<p>CHIP package with body size 1 X 0.5 X 0.55 mm</p>
>NAME
>VALUE
CHIP, 1 X 0.5 X 0.55 mm body
<p>CHIP package with body size 1 X 0.5 X 0.55 mm</p>
16-SOIC, 1.27 mm pitch, 10.32 mm span, 10.30 X 7.50 X 2.65 mm body
<p>16-pin SOIC package with 1.27 mm pitch, 10.32 mm span with body size 10.30 X 7.50 X 2.65 mm</p>
>NAME
>VALUE
16-SOIC, 1.27 mm pitch, 10.32 mm span, 10.30 X 7.50 X 2.65 mm body
<p>16-pin SOIC package with 1.27 mm pitch, 10.32 mm span with body size 10.30 X 7.50 X 2.65 mm</p>
Single-row, 6-pin Pin Header (Male) Right Angle, 2.54 mm (0.10 in) col pitch, 5.84 mm mating length, 15.24 X 2.54 X 2.54 mm body
<p>Single-row (1X6), 6-pin Pin Header (Male) Right Angle package with 2.54 mm (0.10 in) col pitch, 0.64 mm lead width, 2.54 mm tail length and 5.84 mm mating length with body size 15.24 X 2.54 X 2.54 mm, pin pattern - zigzag from bottom left</p>
>NAME
>VALUE
Single-row, 6-pin Pin Header (Male) Right Angle, 2.54 mm (0.10 in) col pitch, 5.84 mm mating length, 15.24 X 2.54 X 2.54 mm body
<p>Single-row (1X6), 6-pin Pin Header (Male) Right Angle package with 2.54 mm (0.10 in) col pitch, 0.64 mm lead width, 2.54 mm tail length and 5.84 mm mating length with body size 15.24 X 2.54 X 2.54 mm, pin pattern - zigzag from bottom left</p>
CHIP, 1 X 0.5 X 0.35 mm body
<p>CHIP package with body size 1 X 0.5 X 0.35 mm</p>
>NAME
>VALUE
CHIP, 1 X 0.5 X 0.35 mm body
<p>CHIP package with body size 1 X 0.5 X 0.35 mm</p>
<b>OSH Park Design Rules</b>
<p>
Please make sure your boards conform to these design rules.
</p>
<p>
Note, that not all DRC settings must be set by the manufacturer. Several can be adjusted for the design, including those listed on our docs page here.
<a href="http://docs.oshpark.com/design-tools/eagle/design-rules-files/">Adjustable Settings</a>
</p>
Since Version 8.3, EAGLE supports Fusion synchronisation.
This feature will not be available in this version and saving
the document will break the link to the Fusion PCB feature.
Since Version 8.3, EAGLE supports URNs for individual library
assets (packages, symbols, and devices). The URNs of those assets
will not be understood (or retained) with this version.
Since Version 8.3, EAGLE supports the association of 3D packages
with devices in libraries, schematics, and board files. Those 3D
packages will not be understood (or retained) with this version.