(kicad_pcb (version 4) (host pcbnew 4.0.6)
  (general
    (links 1)
    (no_connects 0)
    (area 141.955 103.094999 148.545 125.71)
    (thickness 1.6)
    (drawings 380)
    (tracks 1)
    (zones 0)
    (modules 4)
    (nets 2)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFFFF)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 "Net-(H1-Pad1)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(H1-Pad1)")
  )
  (module Pin_Headers:Pin_Header_Angled_1x01_Pitch2.54mm (layer F.Cu) (tedit 59650532)
    (at 146.24 55.65 270)
    (descr "Through hole angled pin header, 1x01, 2.54mm pitch, 6mm pin length, single row")
    (tags "Through hole angled pin header THT 1x01 2.54mm single row")
    (fp_text reference J1 (at 4.385 -2.27 270) (layer F.SilkS))
    (fp_text value CONN_01X01 (at 4.385 2.27 270) (layer F.Fab))
    (fp_text user %R (at 2.77 0 360) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 "Net-(H1-Pad1)"))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x01_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module ownparts:4mmRndPad (layer F.Cu) (tedit 596FF6C4)
    (at 136.64 130.06)
    (fp_text reference H1 (at 0 0.5) (layer F.SilkS))
    (fp_text value Heel (at -0.1 -1.6) (layer F.Fab))
    (pad 1 smd circle (at 0.1 6.5) (size 4 4) (layers F.Cu F.Paste F.Mask)
      (net 1 "Net-(H1-Pad1)"))
  )
  (module sonassist:outlinesL (layer F.Cu) (tedit 0)
    (at 120.65 53.52)
    (fp_text reference outlinesL** (at 0 0) (layer F.SilkS) hide)
    (fp_text value outlinesL (at 0.75 0) (layer F.SilkS) hide)
  )
  (module BIRU:heelPadLCU (layer F.Cu) (tedit 596F9C87)
    (at 126.86 148.02)
    (fp_text reference G*** (at -31.4 0.6) (layer F.Cu) hide)
    (fp_text value heelPadLCU (at -29.3 -2) (layer F.Cu) hide)
  )
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