(kicad_pcb (version 20171130) (host pcbnew "(5.1.9)-1")
  (general
    (thickness 1.6)
    (drawings 19)
    (tracks 65)
    (zones 0)
    (modules 8)
    (nets 26)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.1524)
    (trace_clearance 0.1524)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.1524)
    (via_size 0.508)
    (via_drill 0.254)
    (via_min_size 0.508)
    (via_min_drill 0.254)
    (uvia_size 0.508)
    (uvia_drill 0.254)
    (uvias_allowed no)
    (uvia_min_size 0)
    (uvia_min_drill 0)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.0508)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFFFF)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes true)
      (usegerberadvancedattributes true)
      (creategerberjobfile true)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 GND)
  (net 2 BOOST_OUT)
  (net 3 3.3_Reg)
  (net 4 "Net-(C3-Pad1)")
  (net 5 SCLK)
  (net 6 SDO)
  (net 7 SDI)
  (net 8 *CS)
  (net 9 FPGA_3.3)
  (net 10 SIGNAL)
  (net 11 "Net-(U1-Pad1)")
  (net 12 "Net-(U1-Pad2)")
  (net 13 "Net-(U1-Pad3)")
  (net 14 "Net-(U1-Pad4)")
  (net 15 "Net-(U1-Pad5)")
  (net 16 "Net-(U1-Pad6)")
  (net 17 "Net-(U1-Pad16)")
  (net 18 "Net-(U1-Pad17)")
  (net 19 "Net-(U2-Pad4)")
  (net 20 "Net-(J1-Pad11)")
  (net 21 "Net-(J1-Pad9)")
  (net 22 "Net-(J1-Pad7)")
  (net 23 "Net-(J1-Pad5)")
  (net 24 "Net-(J1-Pad3)")
  (net 25 "Net-(J1-Pad1)")
  (net_class Default "This is the default net class."
    (clearance 0.1524)
    (trace_width 0.1524)
    (via_dia 0.508)
    (via_drill 0.254)
    (uvia_dia 0.508)
    (uvia_drill 0.254)
    (add_net *CS)
    (add_net 3.3_Reg)
    (add_net BOOST_OUT)
    (add_net FPGA_3.3)
    (add_net GND)
    (add_net "Net-(C3-Pad1)")
    (add_net "Net-(J1-Pad1)")
    (add_net "Net-(J1-Pad11)")
    (add_net "Net-(J1-Pad3)")
    (add_net "Net-(J1-Pad5)")
    (add_net "Net-(J1-Pad7)")
    (add_net "Net-(J1-Pad9)")
    (add_net "Net-(U1-Pad1)")
    (add_net "Net-(U1-Pad16)")
    (add_net "Net-(U1-Pad17)")
    (add_net "Net-(U1-Pad2)")
    (add_net "Net-(U1-Pad3)")
    (add_net "Net-(U1-Pad4)")
    (add_net "Net-(U1-Pad5)")
    (add_net "Net-(U1-Pad6)")
    (add_net "Net-(U2-Pad4)")
    (add_net SCLK)
    (add_net SDI)
    (add_net SDO)
    (add_net SIGNAL)
  )
  (module TLA2518:TLA2518IRTER (layer F.Cu) (tedit 0)
    (at 97.15 70.35 180)
    (fp_text reference U1 (at 3.678 -0.008 90) (layer F.SilkS))
    (fp_text value TLA2518IRTER (at -0.508 -3.048 180) (layer F.Fab))
    (fp_text user "Copyright 2016 Accelerated Designs. All rights reserved." (at 0 -2.54) (layer Cmts.User))
    (fp_text user * (at -1.0668 -1) (layer F.Fab))
    (fp_text user * (at -1.0668 -1) (layer F.Fab))
    (pad 1 smd rect (at -1.4732 -0.750001 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 11 "Net-(U1-Pad1)"))
    (pad 2 smd rect (at -1.4732 -0.25 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 12 "Net-(U1-Pad2)"))
    (pad 3 smd rect (at -1.4732 0.25 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 13 "Net-(U1-Pad3)"))
    (pad 4 smd rect (at -1.4732 0.750001 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 14 "Net-(U1-Pad4)"))
    (pad 5 smd rect (at -0.750001 1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 15 "Net-(U1-Pad5)"))
    (pad 6 smd rect (at -0.25 1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 16 "Net-(U1-Pad6)"))
    (pad 7 smd rect (at 0.25 1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 3 3.3_Reg))
    (pad 8 smd rect (at 0.750001 1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 4 "Net-(C3-Pad1)"))
    (pad 9 smd rect (at 1.4732 0.750001 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 10 smd rect (at 1.4732 0.25 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 3 3.3_Reg))
    (pad 11 smd rect (at 1.4732 -0.25 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 8 *CS))
    (pad 12 smd rect (at 1.4732 -0.750001 270) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 6 SDO))
    (pad 13 smd rect (at 0.750001 -1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 5 SCLK))
    (pad 14 smd rect (at 0.25 -1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 7 SDI))
    (pad 15 smd rect (at -0.25 -1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 10 SIGNAL))
    (pad 16 smd rect (at -0.750001 -1.4732 180) (size 0.254 0.8128) (layers F.Cu F.Paste F.Mask)
      (net 17 "Net-(U1-Pad16)"))
    (pad 17 smd rect (at 0 0 180) (size 1.6764 1.6764) (layers F.Cu F.Paste F.Mask)
      (net 18 "Net-(U1-Pad17)"))
  )
  (module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC)
    (at 102.616 66.04)
    (descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x03 2.54mm single row")
    (fp_text reference J3 (at 0 7.366) (layer F.SilkS))
    (fp_text value To_Electrode_IO (at 0 0.762 90) (layer F.Fab))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 10 SIGNAL))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 3.3_Reg))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Connector_PinSocket_2.54mm:PinSocket_1x03_P2.54mm_Horizontal (layer F.Cu) (tedit 5A19A429)
    (at 106.68 71.12 180)
    (descr "Through hole angled socket strip, 1x03, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated")
    (tags "Through hole angled socket strip THT 1x03 2.54mm single row")
    (fp_text reference J2 (at -1.524 -2.286) (layer F.SilkS))
    (fp_text value To_Boost_Converter (at -5.334 2.286) (layer F.Fab))
    (fp_text user %R (at -5.775 2.54) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 9 FPGA_3.3))
    (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 3 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 BOOST_OUT))
    (model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x03_P2.54mm_Horizontal.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5F68FEEE)
    (at 99.796 62.568 180)
    (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
    (tags capacitor)
    (attr smd)
    (fp_text reference C1 (at -0.788 -1.186) (layer F.SilkS))
    (fp_text value 1u (at 0 1.43) (layer F.Fab))
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 1 smd roundrect (at -0.775 0 180) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 GND))
    (pad 2 smd roundrect (at 0.775 0 180) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 2 BOOST_OUT))
    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5F68FEEE)
    (at 99.06 65.265 270)
    (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
    (tags capacitor)
    (attr smd)
    (fp_text reference C2 (at 2.299 0 180) (layer F.SilkS))
    (fp_text value 1u (at 0 1.43 90) (layer F.Fab))
    (fp_text user %R (at 0 0 90) (layer F.Fab))
    (pad 2 smd roundrect (at 0.775 0 270) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 3 3.3_Reg))
    (pad 1 smd roundrect (at -0.775 0 270) (size 0.9 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 GND))
    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitor_SMD:C_0603_1608Metric (layer B.Cu) (tedit 5F68FEEE)
    (at 97.15 70.45 270)
    (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
    (tags capacitor)
    (attr smd)
    (fp_text reference C3 (at 0 1.43 270) (layer B.SilkS))
    (fp_text value 1u (at 0 -1.43 270) (layer B.Fab))
    (fp_text user %R (at 0 0 270) (layer B.Fab))
    (pad 1 smd roundrect (at -0.775 0 270) (size 0.9 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
      (net 4 "Net-(C3-Pad1)"))
    (pad 2 smd roundrect (at 0.775 0 270) (size 0.9 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
      (net 1 GND))
    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC)
    (at 93.98 78.232 90)
    (descr "Through hole straight pin header, 2x06, 2.54mm pitch, double rows")
    (tags "Through hole pin header THT 2x06 2.54mm double row")
    (fp_text reference J1 (at 1.27 -2.33 90) (layer F.SilkS))
    (fp_text value To_FPGA (at 1.27 6.348 180) (layer F.Fab))
    (fp_text user %R (at 1.27 6.35) (layer F.Fab))
    (pad 12 thru_hole oval (at 2.54 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 9 FPGA_3.3))
    (pad 11 thru_hole oval (at 0 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 20 "Net-(J1-Pad11)"))
    (pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 9 thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 21 "Net-(J1-Pad9)"))
    (pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 7 SDI))
    (pad 7 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 22 "Net-(J1-Pad7)"))
    (pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 SCLK))
    (pad 5 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 23 "Net-(J1-Pad5)"))
    (pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 SDO))
    (pad 3 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 24 "Net-(J1-Pad3)"))
    (pad 2 thru_hole oval (at 2.54 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 8 *CS))
    (pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 25 "Net-(J1-Pad1)"))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x06_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Package_TO_SOT_SMD:SOT-23-5 (layer F.Cu) (tedit 5A02FF57)
    (at 95.504 64.643 270)
    (descr "5-pin SOT23 package")
    (tags SOT-23-5)
    (attr smd)
    (fp_text reference U2 (at 0 2.667 90) (layer F.SilkS))
    (fp_text value AP2112K-3.3 (at 0 2.9 90) (layer F.Fab))
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 1 smd rect (at -1.1 -0.95 270) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
      (net 2 BOOST_OUT))
    (pad 2 smd rect (at -1.1 0 270) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 3 smd rect (at -1.1 0.95 270) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
      (net 2 BOOST_OUT))
    (pad 4 smd rect (at 1.1 0.95 270) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
      (net 19 "Net-(U2-Pad4)"))
    (pad 5 smd rect (at 1.1 -0.95 270) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
      (net 3 3.3_Reg))
    (model ${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-23-5.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_text *CS (at 93.98 73.914) (layer B.SilkS))
  (gr_text SDO (at 96.52 73.914) (layer B.SilkS))
  (gr_text SCLK (at 99.06 73.914) (layer B.SilkS))
  (gr_text SDI (at 101.6 73.914) (layer B.SilkS))
  (gr_text GND (at 104.14 73.8886) (layer B.SilkS))
  (gr_text PWR (at 106.68 73.914) (layer B.SilkS))
  (gr_text Vin (at 109.22 71.12) (layer B.SilkS))
  (gr_text GND (at 109.22 68.58) (layer B.SilkS))
  (gr_text Vout (at 109.728 66.04) (layer B.SilkS))
  (gr_text OUT (at 100.076 71.12) (layer B.SilkS))
  (gr_text 3.3V (at 99.9363 68.58762) (layer B.SilkS))
  (gr_text GND (at 100.076 66.04) (layer B.SilkS))
  (gr_text "Designed by Tyler Zhang" (at 106.68 62.9) (layer B.SilkS))
  (gr_line (start 90.424 80.264) (end 90.424 80.01) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 116.84 80.01) (end 116.84 80.264) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 116.84 80.264) (end 90.424 80.264) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 90.424 60.706) (end 116.84 60.706) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 116.84 60.706) (end 116.84 80.01) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 90.424 80.01) (end 90.424 60.706) (layer Edge.Cuts) (width 0.05))
  (zone (net 0) (net_name "") (layer F.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 117.475 80.645) (xy 84.455 80.645) (xy 84.455 52.705) (xy 117.475 52.705)
      )
    )
  )
  (zone (net 1) (net_name GND) (layer B.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 118.11 81.28) (xy 83.82 81.28) (xy 83.82 52.07) (xy 118.11 52.07)
      )
    )
  )
)
