Altium

Design Rule Verification Report

Date	:	3/11/2016
Time	:	7:57:30 PM
Elapsed Time	:	00:00:00
Filename	:	C:\Users\podonoghue\Documents\Development\T962a_Oven_Controller\Hardware\T962a_Panel\T962a_Panel.PcbDoc

Warnings	:	2
Rule Violations	:	0

Summary

Warnings	Count
2 Net Ties failed verification	2
Total	2

Rule Violations	Count
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (IsVia)	0
Room T962a_Panel (Bounding Region = (803.346mil, 191.102mil, 3952.953mil, 1451.102mil) (InComponentClass('T962a_Panel'))	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Net Antennae (Tolerance=0mil) (All)	0
Silk primitive without silk layer	0
Silk to Silk (Clearance=10mil) (All),(All)	0
Silk To Solder Mask (Clearance=5mil) (IsPad),(All)	0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Hole Size Constraint (Min=1mil) (Max=350mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Width Constraint (Min=10mil) (Max=40mil) (Preferred=10mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Clearance Constraint (Gap=6mil) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Total	0

Warnings

2 Net Ties failed verification
SMT Small Component S1-Link3Closed (101mil,-170mil) on Bottom Layer, SMT Small Component S1-Link3Closed (101mil,-170mil) on Bottom Layer, has isolated copper
SMT Small Component S2-Link3Closed (0mil,-170mil) on Bottom Layer, SMT Small Component S2-Link3Closed (0mil,-170mil) on Bottom Layer, has isolated copper