Altium

Design Rule Verification Report

Date	:	4/11/2016
Time	:	2:10:27 PM
Elapsed Time	:	00:00:01
Filename	:	C:\Users\podonoghue\Documents\Development\T962a_Oven_Controller\Hardware\T962a\T962a.PcbDoc

Warnings	:	1
Rule Violations	:	0

Summary

Warnings	Count
1 Net Tie failed verification	1
Total	1

Rule Violations	Count
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Clearance Constraint (Gap=0.178mm) (All),(All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Width Constraint (Min=0.254mm) (Max=1.016mm) (Preferred=0.254mm) (All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=2539.975mm) (All)	0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0.1mm) (Disabled)(All),(All)	0
Silk To Solder Mask (Clearance=0.2mm) (IsPad),(All)	0
Silk to Silk (Clearance=0.254mm) (All),(All)	0
Silk primitive without silk layer	0
Net Antennae (Tolerance=0mm) (All)	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Room T962a-P1 (Bounding Region = (4.03mm, 5.554mm, 106.341mm, 79.804mm) (InComponentClass('T962a-P1'))	0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (IsVia)	0
Clearance Constraint (Gap=0.254mm) (InPoly),(All)	0
Total	0

Warnings

1 Net Tie failed verification
SMT Small Component L5-LinkOpen (-2.54mm,2.54mm) on Top Layer, SMT Small Component L5-LinkOpen (-2.54mm,2.54mm) on Top Layer, has isolated copper