(kicad_pcb (version 4) (host pcbnew 4.0.6)
  (general
    (links 34)
    (no_connects 0)
    (area 140.767999 96.444999 156.412001 110.692001)
    (thickness 1.6)
    (drawings 21)
    (tracks 234)
    (zones 0)
    (modules 8)
    (nets 17)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user hide)
    (49 F.Fab user hide)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 VCC)
  (net 2 GND)
  (net 3 /~CTSI)
  (net 4 /TXDO)
  (net 5 /RXDI)
  (net 6 /~RTSO)
  (net 7 /U2_CTS)
  (net 8 /U2_RX)
  (net 9 /U2_RTS)
  (net 10 /U2_TX)
  (net 11 /PTX)
  (net 12 /PRX)
  (net 13 /PFL_O)
  (net 14 /PFL_I)
  (net 15 "Net-(U1-Pad4)")
  (net 16 "Net-(U1-Pad11)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net /PFL_I)
    (add_net /PFL_O)
    (add_net /PRX)
    (add_net /PTX)
    (add_net /RXDI)
    (add_net /TXDO)
    (add_net /U2_CTS)
    (add_net /U2_RTS)
    (add_net /U2_RX)
    (add_net /U2_TX)
    (add_net /~CTSI)
    (add_net /~RTSO)
    (add_net GND)
    (add_net "Net-(U1-Pad11)")
    (add_net "Net-(U1-Pad4)")
    (add_net VCC)
  )
  (module Pin_Headers:Pin_Header_Angled_1x06_Pitch2.54mm (layer B.Cu) (tedit 597E41E4)
    (at 142.24 109.22 270)
    (descr "Through hole angled pin header, 1x06, 2.54mm pitch, 6mm pin length, single row")
    (tags "Through hole angled pin header THT 1x06 2.54mm single row")
    (fp_text reference J1 (at 4.385 2.27 270) (layer B.SilkS) hide)
    (fp_text value TTLUART (at 4.385 -14.97 270) (layer B.Fab) hide)
    (fp_text user %R (at 2.77 -6.35 540) (layer B.Fab))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 GND))
    (pad 2 thru_hole oval (at 0 -2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 /~CTSI))
    (pad 3 thru_hole oval (at 0 -5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 VCC))
    (pad 4 thru_hole oval (at 0 -7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 /TXDO))
    (pad 5 thru_hole oval (at 0 -10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 /RXDI))
    (pad 6 thru_hole oval (at 0 -12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 /~RTSO))
  )
  (module Resistors_SMD:R_Array_Convex_4x0603 (layer B.Cu) (tedit 597E41FB)
    (at 151.384 104.14 270)
    (descr "Chip Resistor Network, ROHM MNR14 (see mnr_g.pdf)")
    (tags "resistor array")
    (attr smd)
    (fp_text reference RN1 (at 0 2.8 270) (layer B.SilkS) hide)
    (fp_text value 4k7 (at 0 -2.8 270) (layer B.Fab))
    (fp_text user %R (at 0 0 540) (layer B.Fab))
    (pad 1 smd rect (at -0.9 1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 11 /PTX))
    (pad 3 smd rect (at -0.9 -0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 8 /U2_RX))
    (pad 2 smd rect (at -0.9 0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 8 /U2_RX))
    (pad 4 smd rect (at -0.9 -1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 8 /U2_RX))
    (pad 7 smd rect (at 0.9 0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 2 GND))
    (pad 8 smd rect (at 0.9 1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 1 VCC))
    (pad 6 smd rect (at 0.9 -0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 12 /PRX))
    (pad 5 smd rect (at 0.9 -1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 12 /PRX))
    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_Array_Convex_4x0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 597E4204)
    (at 154.178 104.267 90)
    (descr "Capacitor SMD 0603, hand soldering")
    (tags "capacitor 0603")
    (attr smd)
    (fp_text reference C1 (at 0 -1.25 90) (layer F.SilkS) hide)
    (fp_text value 0.1u (at 0 1.5 90) (layer F.Fab))
    (fp_text user %R (at 0 -1.25 90) (layer F.Fab))
    (pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 1 VCC))
    (pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 2 GND))
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module tblayout:TBLAYOUT-ASTRON (layer B.Cu) (tedit 597E41ED)
    (at 148.59 96.544 180)
    (fp_text reference J2 (at 0 0.8 180) (layer B.SilkS) hide)
    (fp_text value TBLAYOUT (at -5.5 -0.8 180) (layer B.SilkS) hide)
    (pad 1 smd rect (at 3 -1.5 180) (size 0.75 3) (layers F.Cu F.Paste F.Mask))
    (pad 2 smd rect (at 2 -1.5 180) (size 0.75 3) (layers F.Cu F.Paste F.Mask)
      (net 7 /U2_CTS))
    (pad 3 smd rect (at 1 -1.5 180) (size 0.75 3) (layers F.Cu F.Paste F.Mask))
    (pad 4 smd rect (at 0 -1.5 180) (size 0.75 3) (layers F.Cu F.Paste F.Mask))
    (pad 5 smd rect (at -1 -1.5 180) (size 0.75 3) (layers F.Cu F.Paste F.Mask))
    (pad 6 smd rect (at -2 -1.5 180) (size 0.75 3) (layers F.Cu F.Paste F.Mask)
      (net 2 GND))
    (pad 7 smd rect (at -3 -1.5 180) (size 0.75 3) (layers F.Cu F.Paste F.Mask))
    (pad 8 smd rect (at 3 -1.5 180) (size 0.75 3) (layers B.Cu B.Paste B.Mask))
    (pad 9 smd rect (at 2 -1.5 180) (size 0.75 3) (layers B.Cu B.Paste B.Mask)
      (net 8 /U2_RX))
    (pad 10 smd rect (at 1 -1.5 180) (size 0.75 3) (layers B.Cu B.Paste B.Mask)
      (net 9 /U2_RTS))
    (pad 11 smd rect (at 0 -1.5 180) (size 0.75 3) (layers B.Cu B.Paste B.Mask)
      (net 10 /U2_TX))
    (pad 12 smd rect (at -1 -1.5 180) (size 0.75 3) (layers B.Cu B.Paste B.Mask))
    (pad 13 smd rect (at -2 -1.5 180) (size 0.75 3) (layers B.Cu B.Paste B.Mask)
      (net 1 VCC))
    (pad 14 smd rect (at -3 -1.5 180) (size 0.75 3) (layers B.Cu B.Paste B.Mask))
  )
  (module Resistors_SMD:R_Array_Convex_4x0603 (layer B.Cu) (tedit 597E4208)
    (at 145.796 104.14 270)
    (descr "Chip Resistor Network, ROHM MNR14 (see mnr_g.pdf)")
    (tags "resistor array")
    (attr smd)
    (fp_text reference RN2 (at 0 2.8 270) (layer B.SilkS) hide)
    (fp_text value 4k7 (at 0 -2.8 270) (layer B.Fab))
    (fp_text user %R (at 0.635 0 540) (layer B.Fab))
    (pad 1 smd rect (at -0.9 1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 13 /PFL_O))
    (pad 3 smd rect (at -0.9 -0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 7 /U2_CTS))
    (pad 2 smd rect (at -0.9 0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 7 /U2_CTS))
    (pad 4 smd rect (at -0.9 -1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 7 /U2_CTS))
    (pad 7 smd rect (at 0.9 0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 2 GND))
    (pad 8 smd rect (at 0.9 1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 1 VCC))
    (pad 6 smd rect (at 0.9 -0.4 270) (size 0.8 0.4) (layers B.Cu B.Paste B.Mask)
      (net 14 /PFL_I))
    (pad 5 smd rect (at 0.9 -1.2 270) (size 0.8 0.5) (layers B.Cu B.Paste B.Mask)
      (net 14 /PFL_I))
    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_Array_Convex_4x0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Housings_SOIC:SOIC-14_3.9x8.7mm_Pitch1.27mm (layer F.Cu) (tedit 597E4213)
    (at 148.59 104.14 270)
    (descr "14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
    (tags "SOIC 1.27")
    (attr smd)
    (fp_text reference U1 (at 0 -5.375 270) (layer F.SilkS) hide)
    (fp_text value 74LVC14A (at 0 5.375 270) (layer F.Fab))
    (fp_text user %R (at -0.0381 0 270) (layer F.Fab))
    (pad 1 smd rect (at -2.7 -3.81 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 11 /PTX))
    (pad 2 smd rect (at -2.7 -2.54 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 4 /TXDO))
    (pad 3 smd rect (at -2.7 -1.27 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 5 /RXDI))
    (pad 4 smd rect (at -2.7 0 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 15 "Net-(U1-Pad4)"))
    (pad 5 smd rect (at -2.7 1.27 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 15 "Net-(U1-Pad4)"))
    (pad 6 smd rect (at -2.7 2.54 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 12 /PRX))
    (pad 7 smd rect (at -2.7 3.81 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 2 GND))
    (pad 8 smd rect (at 2.7 3.81 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 6 /~RTSO))
    (pad 9 smd rect (at 2.7 2.54 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 13 /PFL_O))
    (pad 10 smd rect (at 2.7 1.27 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 14 /PFL_I))
    (pad 11 smd rect (at 2.7 0 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 16 "Net-(U1-Pad11)"))
    (pad 12 smd rect (at 2.7 -1.27 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 16 "Net-(U1-Pad11)"))
    (pad 13 smd rect (at 2.7 -2.54 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 3 /~CTSI))
    (pad 14 smd rect (at 2.7 -3.81 270) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
      (net 1 VCC))
    (model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-14_3.9x8.7mm_Pitch1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module TO_SOT_Packages_SMD:SOT-323_SC-70_Handsoldering (layer B.Cu) (tedit 597E4200)
    (at 154.94 104.775 270)
    (descr "SOT-323, SC-70 Handsoldering")
    (tags "SOT-323 SC-70 Handsoldering")
    (attr smd)
    (fp_text reference Q1 (at 0 2 270) (layer B.SilkS) hide)
    (fp_text value NX3008NBKW (at 0 -2.05 270) (layer B.Fab) hide)
    (fp_text user %R (at 0 0 540) (layer B.Fab))
    (pad 1 smd rect (at -1.33 0.65) (size 0.45 1.5) (layers B.Cu B.Paste B.Mask)
      (net 10 /U2_TX))
    (pad 2 smd rect (at -1.33 -0.65) (size 0.45 1.5) (layers B.Cu B.Paste B.Mask)
      (net 2 GND))
    (pad 3 smd rect (at 1.33 0) (size 0.45 1.5) (layers B.Cu B.Paste B.Mask)
      (net 11 /PTX))
    (model ${KISYS3DMOD}/TO_SOT_Packages_SMD.3dshapes/SOT-323_SC-70.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module TO_SOT_Packages_SMD:SOT-323_SC-70_Handsoldering (layer B.Cu) (tedit 597E41E9)
    (at 142.24 104.775 270)
    (descr "SOT-323, SC-70 Handsoldering")
    (tags "SOT-323 SC-70 Handsoldering")
    (attr smd)
    (fp_text reference Q2 (at 0 2 270) (layer B.SilkS) hide)
    (fp_text value NX3008NBKW (at 0 -2.05 270) (layer B.Fab))
    (fp_text user %R (at 0 0 540) (layer B.Fab))
    (pad 1 smd rect (at -1.33 0.65) (size 0.45 1.5) (layers B.Cu B.Paste B.Mask)
      (net 9 /U2_RTS))
    (pad 2 smd rect (at -1.33 -0.65) (size 0.45 1.5) (layers B.Cu B.Paste B.Mask)
      (net 2 GND))
    (pad 3 smd rect (at 1.33 0) (size 0.45 1.5) (layers B.Cu B.Paste B.Mask)
      (net 13 /PFL_O))
    (model ${KISYS3DMOD}/TO_SOT_Packages_SMD.3dshapes/SOT-323_SC-70.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_text RX (at 152.4 107.442) (layer B.SilkS))
  (gr_text TX (at 149.86 107.442) (layer B.SilkS))
  (dimension 14.097 (width 0.3) (layer Dwgs.User)
    (gr_text "14.097 mm" (at 137.08 103.5685 90) (layer Dwgs.User))
    (feature1 (pts (xy 140.462 96.52) (xy 135.73 96.52)))
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    (arrow2a (pts (xy 138.43 110.617) (xy 139.016421 109.490496)))
    (arrow2b (pts (xy 138.43 110.617) (xy 137.843579 109.490496)))
  )
  (dimension 15.494 (width 0.3) (layer Dwgs.User)
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    (feature1 (pts (xy 156.337 111.252) (xy 156.337 115.095)))
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    (arrow2b (pts (xy 140.843 112.395) (xy 141.969504 111.808579)))
  )
  (gr_line (start 153.543 99.441) (end 156.337 102.235) (layer Edge.Cuts) (width 0.15))
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  (gr_line (start 153.543 99.441) (end 152.527 98.425) (layer Edge.Cuts) (width 0.15))
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  (gr_line (start 140.843 110.363) (end 141.097 110.617) (layer Edge.Cuts) (width 0.15))
  (zone (net 2) (net_name GND) (layer F.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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      )
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  )
  (zone (net 2) (net_name GND) (layer B.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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      (pts
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      )
    )
  )
)
