(kicad_pcb (version 4) (host pcbnew 4.0.7)
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    (no_connects 0)
    (area 92.634999 73.584999 115.645001 91.515001)
    (thickness 1.6)
    (drawings 18)
    (tracks 8)
    (zones 0)
    (modules 3)
    (nets 9)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
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    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
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    (via_drill 0.4)
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    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
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    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
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      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
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      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 "Net-(P1-Pad1)")
  (net 2 "Net-(P1-Pad2)")
  (net 3 "Net-(P1-Pad3)")
  (net 4 "Net-(P1-Pad4)")
  (net 5 "Net-(P2-Pad8)")
  (net 6 "Net-(P2-Pad2)")
  (net 7 "Net-(P2-Pad4)")
  (net 8 "Net-(P2-Pad6)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(P1-Pad1)")
    (add_net "Net-(P1-Pad2)")
    (add_net "Net-(P1-Pad3)")
    (add_net "Net-(P1-Pad4)")
    (add_net "Net-(P2-Pad2)")
    (add_net "Net-(P2-Pad4)")
    (add_net "Net-(P2-Pad6)")
    (add_net "Net-(P2-Pad8)")
  )
  (module Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm (layer F.Cu) (tedit 5A11F075)
    (at 96.52 78.74)
    (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x04 2.54mm single row")
    (fp_text reference P1 (at 0 -2.33) (layer F.SilkS) hide)
    (fp_text value CONN_4 (at 0 9.95) (layer F.Fab) hide)
    (fp_text user %R (at 0 3.81 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 "Net-(P1-Pad1)"))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 "Net-(P1-Pad2)"))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 "Net-(P1-Pad3)"))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 "Net-(P1-Pad4)"))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x04_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module w_conn_strip:vasch_strip_4x2 (layer F.Cu) (tedit 5A11F07F)
    (at 104.14 82.55 270)
    (descr "Box header 4x2pin 2.54mm")
    (tags "CONN DEV")
    (fp_text reference P2 (at 0 -5.7 270) (layer F.SilkS) hide)
    (fp_text value MY_CONN_I2C (at 0 5.7 270) (layer F.SilkS) hide)
    (pad 8 thru_hole oval (at 3.81 -1.27 270) (size 1.5 2) (drill 1 (offset 0 -0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 5 "Net-(P2-Pad8)"))
    (pad 7 thru_hole oval (at 3.81 1.27 270) (size 1.5 2) (drill 1 (offset 0 0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 4 "Net-(P1-Pad4)"))
    (pad 1 thru_hole rect (at -3.81 1.27 270) (size 1.5 2) (drill 1 (offset 0 0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 1 "Net-(P1-Pad1)"))
    (pad 2 thru_hole oval (at -3.81 -1.27 270) (size 1.5 2) (drill 1 (offset 0 -0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 6 "Net-(P2-Pad2)"))
    (pad 3 thru_hole oval (at -1.27 1.27 270) (size 1.5 2) (drill 1 (offset 0 0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 2 "Net-(P1-Pad2)"))
    (pad 4 thru_hole oval (at -1.27 -1.27 270) (size 1.5 2) (drill 1 (offset 0 -0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 7 "Net-(P2-Pad4)"))
    (pad 5 thru_hole oval (at 1.27 1.27 270) (size 1.5 2) (drill 1 (offset 0 0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 3 "Net-(P1-Pad3)"))
    (pad 6 thru_hole oval (at 1.27 -1.27 270) (size 1.5 2) (drill 1 (offset 0 -0.25)) (layers *.Cu *.Mask F.SilkS)
      (net 8 "Net-(P2-Pad6)"))
    (model walter/conn_strip/vasch_strip_4x2.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm (layer F.Cu) (tedit 5A11F07C)
    (at 111.76 78.74)
    (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x04 2.54mm single row")
    (fp_text reference P3 (at 0 -2.33) (layer F.SilkS) hide)
    (fp_text value CONN_4 (at 0 9.95) (layer F.Fab) hide)
    (fp_text user %R (at 0 3.81 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 "Net-(P2-Pad2)"))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 7 "Net-(P2-Pad4)"))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 8 "Net-(P2-Pad6)"))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 "Net-(P2-Pad8)"))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x04_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
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    (arrow2b (pts (xy 87.63 91.44) (xy 87.043579 90.313496)))
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)
