Design Rule Verification Report
Date:
12/13/2024
Time:
3:32:54 PM
Elapsed Time:
00:00:01
Filename:
C:\Users\Travis.James\Local\active_Altium\PFC_LCM\LCM_DSM_ESAD_HUB_V3\LCM_DSM_ESAD_HUB_V3.PCBDOC
Warnings:
0
Rule Violations:
0
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=6mil) (All),(All)
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Width Constraint (Min=7mil) (Max=55mil) (Preferred=15mil) (All)
0
Routing Via (MinHoleWidth=14mil) (MaxHoleWidth=120mil) (PreferredHoleWidth=14mil) (MinWidth=31mil) (MaxWidth=120mil) (PreferedWidth=33mil) (All)
0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=25mil) (Air Gap=10mil) (Entries=4) (All)
0
Hole Size Constraint (Min=1mil) (Max=200mil) (All)
0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
0
Total
0
