(kicad_pcb (version 4) (host pcbnew 4.0.7)
  (general
    (links 29)
    (no_connects 0)
    (area 185.344999 76.124999 200.735001 119.455001)
    (thickness 1.6)
    (drawings 4)
    (tracks 101)
    (zones 0)
    (modules 6)
    (nets 17)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 GND)
  (net 2 VCC)
  (net 3 /SER)
  (net 4 /SRCLK)
  (net 5 /RCLK)
  (net 6 /VDD)
  (net 7 /VO)
  (net 8 /RS)
  (net 9 /E)
  (net 10 /D4)
  (net 11 /D5)
  (net 12 /D6)
  (net 13 /D7)
  (net 14 /LED+)
  (net 15 "Net-(RV1-Pad1)")
  (net 16 "Net-(U1-Pad9)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net /D4)
    (add_net /D5)
    (add_net /D6)
    (add_net /D7)
    (add_net /E)
    (add_net /LED+)
    (add_net /RCLK)
    (add_net /RS)
    (add_net /SER)
    (add_net /SRCLK)
    (add_net /VDD)
    (add_net /VO)
    (add_net GND)
    (add_net "Net-(RV1-Pad1)")
    (add_net "Net-(U1-Pad9)")
    (add_net VCC)
  )
  (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 59958EE7)
    (at 195.58 116.84 180)
    (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
    (tags "capacitor 0603")
    (attr smd)
    (fp_text reference C1 (at 0 1.5 180) (layer B.SilkS))
    (fp_text value 0.1uF (at 0 -1.5 180) (layer B.Fab))
    (fp_text user %R (at 0 0 180) (layer B.Fab))
    (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask)
      (net 1 GND))
    (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask)
      (net 2 VCC))
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Pin_Headers:Pin_Header_Angled_1x05_Pitch2.54mm (layer F.Cu) (tedit 59650532)
    (at 193.04 78.74)
    (descr "Through hole angled pin header, 1x05, 2.54mm pitch, 6mm pin length, single row")
    (tags "Through hole angled pin header THT 1x05 2.54mm single row")
    (fp_text reference J1 (at 4.385 -2.27) (layer F.SilkS))
    (fp_text value Conn_01x05 (at 4.385 12.43) (layer F.Fab))
    (fp_text user %R (at 2.77 5.08 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 VCC))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 /SER))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 /SRCLK))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 /RCLK))
    (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x05_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Pin_Headers:Pin_Header_Straight_1x16_Pitch2.54mm (layer F.Cu) (tedit 59650532)
    (at 187.96 78.74)
    (descr "Through hole straight pin header, 1x16, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x16 2.54mm single row")
    (fp_text reference J2 (at 0 -2.33) (layer F.SilkS))
    (fp_text value Conn_01x16 (at 0 40.43) (layer F.Fab))
    (fp_text user %R (at 0 19.05 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 /VDD))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 7 /VO))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 8 /RS))
    (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 9 /E))
    (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 11 thru_hole oval (at 0 25.4) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 10 /D4))
    (pad 12 thru_hole oval (at 0 27.94) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 11 /D5))
    (pad 13 thru_hole oval (at 0 30.48) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 12 /D6))
    (pad 14 thru_hole oval (at 0 33.02) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 13 /D7))
    (pad 15 thru_hole oval (at 0 35.56) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 14 /LED+))
    (pad 16 thru_hole oval (at 0 38.1) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x16_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Potentiometers:Potentiometer_Trimmer_Vishay_TS53YJ (layer F.Cu) (tedit 58826B0B)
    (at 195.58 111.76 180)
    (descr "Spindle Trimmer Potentiometer, Vishay TS53YJ, https://www.bourns.com/pdfs/3224.pdf")
    (tags "Spindle Trimmer Potentiometer   Vishay TS53YJ")
    (attr smd)
    (fp_text reference RV1 (at 0 -3.75 180) (layer F.SilkS))
    (fp_text value 1K (at 0 3.75 180) (layer F.Fab))
    (pad 1 smd rect (at 2 -1.15 180) (size 2 1.3) (layers F.Cu F.Mask)
      (net 15 "Net-(RV1-Pad1)"))
    (pad 2 smd rect (at -2 0 180) (size 2 2) (layers F.Cu F.Mask)
      (net 14 /LED+))
    (pad 3 smd rect (at 2 1.15 180) (size 2 1.3) (layers F.Cu F.Mask)
      (net 14 /LED+))
    (model Potentiometers.3dshapes/Potentiometer_Trimmer_Vishay_TS53YJ.wrl
      (at (xyz 0.03 0 0))
      (scale (xyz 0.39 0.39 0.39))
      (rotate (xyz 0 0 0))
    )
  )
  (module Potentiometers:Potentiometer_Trimmer_Vishay_TS53YJ (layer F.Cu) (tedit 58826B0B)
    (at 195.58 96.52 180)
    (descr "Spindle Trimmer Potentiometer, Vishay TS53YJ, https://www.bourns.com/pdfs/3224.pdf")
    (tags "Spindle Trimmer Potentiometer   Vishay TS53YJ")
    (attr smd)
    (fp_text reference RV2 (at 0 -3.75 180) (layer F.SilkS))
    (fp_text value 10K (at 0 3.75 180) (layer F.Fab))
    (pad 1 smd rect (at 2 -1.15 180) (size 2 1.3) (layers F.Cu F.Mask)
      (net 6 /VDD))
    (pad 2 smd rect (at -2 0 180) (size 2 2) (layers F.Cu F.Mask)
      (net 7 /VO))
    (pad 3 smd rect (at 2 1.15 180) (size 2 1.3) (layers F.Cu F.Mask)
      (net 1 GND))
    (model Potentiometers.3dshapes/Potentiometer_Trimmer_Vishay_TS53YJ.wrl
      (at (xyz 0.03 0 0))
      (scale (xyz 0.39 0.39 0.39))
      (rotate (xyz 0 0 0))
    )
  )
  (module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer B.Cu) (tedit 58CC8F64)
    (at 195.58 109.22)
    (descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
    (tags "SOIC 1.27")
    (attr smd)
    (fp_text reference U1 (at 0 6) (layer B.SilkS))
    (fp_text value 74HC595 (at 0 -6) (layer B.Fab))
    (fp_text user %R (at 0 0) (layer B.Fab))
    (pad 1 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 15 "Net-(RV1-Pad1)"))
    (pad 2 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 8 /RS))
    (pad 3 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 9 /E))
    (pad 4 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 13 /D7))
    (pad 5 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 12 /D6))
    (pad 6 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 11 /D5))
    (pad 7 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 10 /D4))
    (pad 8 smd rect (at -2.7 -4.445) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 1 GND))
    (pad 9 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 16 "Net-(U1-Pad9)"))
    (pad 10 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 2 VCC))
    (pad 11 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 4 /SRCLK))
    (pad 12 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 5 /RCLK))
    (pad 13 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 1 GND))
    (pad 14 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 3 /SER))
    (pad 15 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 6 /VDD))
    (pad 16 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
      (net 2 VCC))
    (model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_line (start 200.66 76.2) (end 185.42 76.2) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 200.66 119.38) (end 200.66 76.2) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 185.42 119.38) (end 200.66 119.38) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 185.42 76.2) (end 185.42 119.38) (angle 90) (layer Edge.Cuts) (width 0.15))
  (zone (net 1) (net_name GND) (layer F.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 185.42 76.2) (xy 200.66 76.2) (xy 200.66 119.38) (xy 185.42 119.38)
      )
    )
  )
)
