Altiumcustomize

Design Rule Verification Report

Date : 11/25/2019
Time : 11:00:34 PM
Elapsed Time : 00:00:00
Filename : C:\Users\Reid\Desktop\Final_Amplifier.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Hole To Hole Clearance (Gap=8mil) (All),(All) 0
Hole Size Constraint (Min=10mil) (Max=260mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Width Constraint (Min=8mil) (Max=8mil) (Preferred=8mil) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=8mil) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Total 0