Copyright (c) 2019
by K.C. Lee
CCBY 4.0
<b>Small Shrink Outline Package</b>
>NAME
>VALUE
<b>SMALL OUTLINE INTEGRATED CIRCUIT</b><p>
wide body 7.5 mm/JEDEC MS-013AC
>NAME
>VALUE
<b>IPC-7351 compliant SMT capacitors</b><br>
<br>
Symbols copied from CadSoft rcl.lbr<br>
Packages generated using genpkg_chp.ulp, genpkg_cae.ulp and genpkg_mld.ulp<br>
Devices are Vishay chip types, generic AEC types and Kemet T491 series molded body types.<br>
<br>
Weartronics 2006<br>
http://www.weartronics.com/
>NAME
>VALUE
<b>Test Pins/Pads</b><p>
Cream on SMD OFF.<br>
new: Attribute TP_SIGNAL_NAME<br>
<author>Created by librarian@cadsoft.de</author>
<b>TEST PAD</b>
>NAME
>VALUE
>TP_SIGNAL_NAME
<b>OSH Park Design Rules</b>
<p>
Please make sure your boards conform to these design rules.
</p>
<p>
Note, that not all DRC settings must be set by the manufacturer. Several can be adjusted for the design, including those listed on our docs page here.
<a href="http://docs.oshpark.com/design-tools/eagle/design-rules-files/">Adjustable Settings</a>
</p>
Since Version 6.2.2 text objects can contain more than one line,
which will not be processed correctly with this version.