Altium

Design Rule Verification Report

Date: 6/8/2017
Time: 6:12:53 PM
Elapsed Time: 00:00:01
Filename: C:\Users\nguyejt\Downloads\UHFCubeSatBoard\UHFCubeSatBoard\UHFCubeSatBoard.PcbDoc
Warnings: 0
Rule Violations: 23

Summary

Warnings Count
Total 0

Rule Violations Count
Width Constraint (Min=6mil) (Max=30mil) (Preferred=10mil) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=0mil) (Disabled)(All),(All) 0
Silk To Solder Mask (Clearance=5mil) (IsPad),(All) 12
Minimum Solder Mask Sliver (Gap=4mil) (All),(All) 11
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=10mil) (Max=260mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Width Constraint (Min=13.5mil) (Max=13.5mil) (Preferred=13.5mil) ((InNet('RF_CANSAT_TX') OR InNet('RF_CC1125_RX') OR InNet('RF_CC1125_TX') OR InNet('RF_CC1125_TX_RX') OR InNet('RF_LNA_IN') OR InNet('RF_PA_OUT') OR InNet('RF_TX_TO_PA'))) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=6mil) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Minimum Annular Ring (Minimum=4mil) (All) 0
Total 23

Silk To Solder Mask (Clearance=5mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (1.856mil < 5mil) Between Track (1971.535mil,1865mil)(2048.307mil,1865mil) on Top Overlay And Pad U3-C1(2009.921mil,1873.78mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.856mil]
Silk To Solder Mask Clearance Constraint: (1.856mil < 5mil) Between Track (1971.535mil,1865mil)(2048.307mil,1865mil) on Top Overlay And Pad U3-E1(1980.394mil,1873.78mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.856mil]
Silk To Solder Mask Clearance Constraint: (1.935mil < 5mil) Between Track (1971.535mil,1865mil)(1971.535mil,1938.622mil) on Top Overlay And Pad U3-E1(1980.394mil,1873.78mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.935mil]
Silk To Solder Mask Clearance Constraint: (1.856mil < 5mil) Between Track (1971.535mil,1865mil)(2048.307mil,1865mil) on Top Overlay And Pad U3-A1(2039.449mil,1873.78mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.856mil]
Silk To Solder Mask Clearance Constraint: (1.935mil < 5mil) Between Track (2048.307mil,1865mil)(2048.307mil,1938.622mil) on Top Overlay And Pad U3-A1(2039.449mil,1873.78mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.935mil]
Silk To Solder Mask Clearance Constraint: (1.935mil < 5mil) Between Track (1971.535mil,1865mil)(1971.535mil,1938.622mil) on Top Overlay And Pad U3-E2(1980.394mil,1897.559mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.935mil]
Silk To Solder Mask Clearance Constraint: (1.856mil < 5mil) Between Track (1971.535mil,1938.622mil)(2048.307mil,1938.622mil) on Top Overlay And Pad U3-B3(2019.764mil,1929.842mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.856mil]
Silk To Solder Mask Clearance Constraint: (1.856mil < 5mil) Between Track (1971.535mil,1938.622mil)(2048.307mil,1938.622mil) on Top Overlay And Pad U3-A3(2039.449mil,1929.842mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.856mil]
Silk To Solder Mask Clearance Constraint: (1.935mil < 5mil) Between Track (2048.307mil,1865mil)(2048.307mil,1938.622mil) on Top Overlay And Pad U3-A3(2039.449mil,1929.842mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.935mil]
Silk To Solder Mask Clearance Constraint: (1.856mil < 5mil) Between Track (1971.535mil,1938.622mil)(2048.307mil,1938.622mil) on Top Overlay And Pad U3-D3(2000.079mil,1929.842mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.856mil]
Silk To Solder Mask Clearance Constraint: (1.856mil < 5mil) Between Track (1971.535mil,1938.622mil)(2048.307mil,1938.622mil) on Top Overlay And Pad U3-E3(1980.394mil,1929.842mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.856mil]
Silk To Solder Mask Clearance Constraint: (1.935mil < 5mil) Between Track (1971.535mil,1865mil)(1971.535mil,1938.622mil) on Top Overlay And Pad U3-E3(1980.394mil,1929.842mil) on RF and Signal Layer 1 [Top Overlay] to [Top Solder] clearance [1.935mil]
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Minimum Solder Mask Sliver (Gap=4mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (3.148mil < 4mil) Between Pad U3-D3(2000.079mil,1929.842mil) on RF and Signal Layer 1 And Pad U3-B3(2019.764mil,1929.842mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.148mil]
Minimum Solder Mask Sliver Constraint: (3.148mil < 4mil) Between Pad U3-A3(2039.449mil,1929.842mil) on RF and Signal Layer 1 And Pad U3-B3(2019.764mil,1929.842mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.148mil]
Minimum Solder Mask Sliver Constraint: (3.148mil < 4mil) Between Pad U3-E3(1980.394mil,1929.842mil) on RF and Signal Layer 1 And Pad U3-D3(2000.079mil,1929.842mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.148mil]
Minimum Solder Mask Sliver Constraint: (1.119mil < 4mil) Between Via (1974.645mil,1612.052mil) from RF and Signal Layer 1 to Signal Layer 2 And Pad U1-5(1981.535mil,1574.252mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [1.119mil]
Minimum Solder Mask Sliver Constraint: (3.858mil < 4mil) Between Pad U11-2(3335mil,754.409mil) on RF and Signal Layer 1 And Pad U11-3(3335mil,728.819mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.858mil]
Minimum Solder Mask Sliver Constraint: (3.858mil < 4mil) Between Pad U11-1(3335mil,780mil) on RF and Signal Layer 1 And Pad U11-2(3335mil,754.409mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.858mil]
Minimum Solder Mask Sliver Constraint: (3.858mil < 4mil) Between Pad U10-2(1785.562mil,2310.157mil) on RF and Signal Layer 1 And Pad U10-3(1811.153mil,2310.157mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.858mil]
Minimum Solder Mask Sliver Constraint: (3.858mil < 4mil) Between Pad U10-1(1759.972mil,2310.157mil) on RF and Signal Layer 1 And Pad U10-2(1785.562mil,2310.157mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.858mil]
Minimum Solder Mask Sliver Constraint: (3.858mil < 4mil) Between Pad U8-2(1900.591mil,3050mil) on RF and Signal Layer 1 And Pad U8-3(1926.181mil,3050mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.858mil]
Minimum Solder Mask Sliver Constraint: (3.858mil < 4mil) Between Pad U8-1(1875mil,3050mil) on RF and Signal Layer 1 And Pad U8-2(1900.591mil,3050mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.858mil]
Minimum Solder Mask Sliver Constraint: (3.717mil < 4mil) Between Via (1433.855mil,1270.117mil) from RF and Signal Layer 1 to Signal Layer 2 And Pad C7-1(1415.315mil,1305mil) on RF and Signal Layer 1 [Top Solder] Mask Sliver [3.717mil]
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