Altium

Design Rule Verification Report

Date: 4/12/2019
Time: 12:59:42 PM
Elapsed Time: 00:00:01
Filename: PCB1.CMPcbDoc
Errors: 0
Warnings: 0
Rule Violations: 0

Summary

Errors Count
0

Warnings Count
0

Rule Violations Count
Unpoured Polygon (Allow unpoured: False) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=5mil) (All),(All) 0
Silk To Solder Mask (Clearance=1mil) (IsPad),(All) 0
Minimum Solder Mask Sliver (Gap=1mil) (All),(All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=8mil) (Max=100mil) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Width Constraint (Min=5mil) (Max=60mil) (Preferred=10mil) (All) 0
Clearance Constraint (Gap=5mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Total
0