(kicad_pcb (version 20171130) (host pcbnew 5.0.0)
  (general
    (thickness 1.6)
    (drawings 6)
    (tracks 86)
    (zones 0)
    (modules 3)
    (nets 25)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user hide)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user hide)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user hide)
    (47 F.CrtYd user)
    (48 B.Fab user hide)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.1778)
    (trace_clearance 0.1778)
    (zone_clearance 0.208)
    (zone_45_only yes)
    (trace_min 0.1778)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.3556)
    (via_drill 0.1016)
    (via_min_size 0.3556)
    (via_min_drill 0.1016)
    (uvia_size 0.1778)
    (uvia_drill 0.0762)
    (uvias_allowed no)
    (uvia_min_size 0.1778)
    (uvia_min_drill 0.0762)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 1.2)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFFF33F)
    (pcbplotparams
      (layerselection 0x010f8_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "gerber/cardedge/"))
  )
  (net 0 "")
  (net 1 GND)
  (net 2 +5V)
  (net 3 PWR_ENABLE)
  (net 4 MIO15)
  (net 5 MIO10)
  (net 6 MIO13)
  (net 7 MIO14)
  (net 8 MIO0)
  (net 9 MIO48)
  (net 10 MIO51)
  (net 11 MIO49)
  (net 12 MIO47)
  (net 13 MIO46)
  (net 14 MIO11)
  (net 15 MIO12)
  (net 16 PG_MODULE)
  (net 17 FPGA_DONE)
  (net 18 "Net-(P5-Pad41)")
  (net 19 "Net-(P5-Pad42)")
  (net 20 "Net-(P5-Pad45)")
  (net 21 "Net-(P5-Pad46)")
  (net 22 "Net-(P5-Pad49)")
  (net 23 "Net-(P5-Pad50)")
  (net 24 "Net-(P5-Pad54)")
  (net_class Default "This is the default net class."
    (clearance 0.1778)
    (trace_width 0.1778)
    (via_dia 0.3556)
    (via_drill 0.1016)
    (uvia_dia 0.1778)
    (uvia_drill 0.0762)
    (add_net +5V)
    (add_net FPGA_DONE)
    (add_net GND)
    (add_net MIO0)
    (add_net MIO10)
    (add_net MIO11)
    (add_net MIO12)
    (add_net MIO13)
    (add_net MIO14)
    (add_net MIO15)
    (add_net MIO46)
    (add_net MIO47)
    (add_net MIO48)
    (add_net MIO49)
    (add_net MIO51)
    (add_net "Net-(P5-Pad41)")
    (add_net "Net-(P5-Pad42)")
    (add_net "Net-(P5-Pad45)")
    (add_net "Net-(P5-Pad46)")
    (add_net "Net-(P5-Pad49)")
    (add_net "Net-(P5-Pad50)")
    (add_net "Net-(P5-Pad54)")
    (add_net PG_MODULE)
    (add_net PWR_ENABLE)
  )
  (module Connectors_Samtec:MECF-30-01-L-DV-WT_Socket (layer F.Cu) (tedit 594BB3DE)
    (at 198.3486 133.3246 90)
    (descr "Highspeed card edge connector for 1.6mm PCB's with 30 contacts (polarized)")
    (tags "conn samtec card-edge high-speed")
    (attr smd)
    (fp_text reference P5 (at 0 3.81 90) (layer F.SilkS))
    (fp_text value CONN_02X30 (at 0 -3.81 90) (layer F.Fab))
    (fp_text user %R (at 0 0 90) (layer F.Fab))
    (pad 1 smd rect (at -18.415 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 2 smd rect (at -18.415 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 3 smd rect (at -17.145 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 4 smd rect (at -17.145 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 5 smd rect (at -15.875 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 9 MIO48))
    (pad 6 smd rect (at -15.875 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 10 MIO51))
    (pad 7 smd rect (at -14.605 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 8 smd rect (at -14.605 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 9 smd rect (at -13.335 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 8 MIO0))
    (pad 10 smd rect (at -13.335 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 11 MIO49))
    (pad 11 smd rect (at -12.065 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 12 smd rect (at -12.065 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 13 smd rect (at -10.795 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 7 MIO14))
    (pad 14 smd rect (at -10.795 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 12 MIO47))
    (pad 15 smd rect (at -9.525 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 16 smd rect (at -9.525 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 17 smd rect (at -8.255 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 6 MIO13))
    (pad 18 smd rect (at -8.255 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 13 MIO46))
    (pad 19 smd rect (at -6.985 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 20 smd rect (at -6.985 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 23 smd rect (at -4.445 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 24 smd rect (at -4.445 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 25 smd rect (at -3.175 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 5 MIO10))
    (pad 26 smd rect (at -3.175 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 14 MIO11))
    (pad 27 smd rect (at -1.905 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 28 smd rect (at -1.905 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 29 smd rect (at -0.635 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 4 MIO15))
    (pad 30 smd rect (at -0.635 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 15 MIO12))
    (pad 31 smd rect (at 0.635 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 32 smd rect (at 0.635 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 33 smd rect (at 1.905 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 2 +5V))
    (pad 34 smd rect (at 1.905 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 2 +5V))
    (pad 35 smd rect (at 3.175 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 36 smd rect (at 3.175 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 37 smd rect (at 4.445 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 2 +5V))
    (pad 38 smd rect (at 4.445 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 2 +5V))
    (pad 39 smd rect (at 5.715 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 40 smd rect (at 5.715 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 41 smd rect (at 6.985 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 18 "Net-(P5-Pad41)"))
    (pad 42 smd rect (at 6.985 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 19 "Net-(P5-Pad42)"))
    (pad 43 smd rect (at 8.255 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 44 smd rect (at 8.255 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 45 smd rect (at 9.525 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 20 "Net-(P5-Pad45)"))
    (pad 46 smd rect (at 9.525 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 21 "Net-(P5-Pad46)"))
    (pad 47 smd rect (at 10.795 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 48 smd rect (at 10.795 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 49 smd rect (at 12.065 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 22 "Net-(P5-Pad49)"))
    (pad 50 smd rect (at 12.065 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 23 "Net-(P5-Pad50)"))
    (pad 51 smd rect (at 13.335 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 52 smd rect (at 13.335 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 53 smd rect (at 14.605 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 16 PG_MODULE))
    (pad 54 smd rect (at 14.605 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 24 "Net-(P5-Pad54)"))
    (pad 55 smd rect (at 15.875 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 56 smd rect (at 15.875 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 57 smd rect (at 17.145 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 3 PWR_ENABLE))
    (pad 58 smd rect (at 17.145 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 17 FPGA_DONE))
    (pad 59 smd rect (at 18.415 1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 60 smd rect (at 18.415 -1.905 90) (size 0.66 1.35) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad "" np_thru_hole circle (at -20.195 0 90) (size 0 0) (drill 1.45) (layers *.Cu *.Mask))
    (pad "" np_thru_hole circle (at 20.195 1 90) (size 0 0) (drill 1.45) (layers *.Cu *.Mask))
    (pad "" thru_hole circle (at -22.1 0 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Mask))
    (pad "" thru_hole circle (at 22.1 0 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Mask))
  )
  (module motherboard:LOGO (layer B.Cu) (tedit 0)
    (at 198.501 113.6142 270)
    (fp_text reference LOGO (at 0 -5 270) (layer B.SilkS) hide)
    (fp_text value "" (at 0 0 270) (layer B.SilkS))
  )
  (module Pin_Headers:Pin_Header_Straight_1x17_Pitch2.54mm (layer F.Cu) (tedit 59650532)
    (at 211.201 153.1874 180)
    (descr "Through hole straight pin header, 1x17, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x17 2.54mm single row")
    (fp_text reference J4 (at 0 -2.33 180) (layer F.SilkS))
    (fp_text value "Cardedge breakout" (at 0 42.97 180) (layer F.Fab))
    (fp_text user %R (at 0 20.32 270) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 +5V))
    (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 10 MIO51))
    (pad 3 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 11 MIO49))
    (pad 4 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 12 MIO47))
    (pad 5 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 13 MIO46))
    (pad 6 thru_hole oval (at 0 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 14 MIO11))
    (pad 7 thru_hole oval (at 0 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 15 MIO12))
    (pad 8 thru_hole oval (at 0 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 9 MIO48))
    (pad 9 thru_hole oval (at 0 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 8 MIO0))
    (pad 10 thru_hole oval (at 0 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 7 MIO14))
    (pad 11 thru_hole oval (at 0 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 MIO13))
    (pad 12 thru_hole oval (at 0 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 MIO10))
    (pad 13 thru_hole oval (at 0 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 MIO15))
    (pad 14 thru_hole oval (at 0 33.02 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 PWR_ENABLE))
    (pad 15 thru_hole oval (at 0 35.56 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 16 PG_MODULE))
    (pad 16 thru_hole oval (at 0 38.1 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 17 FPGA_DONE))
    (pad 17 thru_hole oval (at 0 40.64 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x17_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_line (start 213.9442 158.115) (end 213.9442 105.537) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 194.183 158.115) (end 213.9442 158.115) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 213.9442 105.537) (end 194.183 105.537) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 194.183 105.537) (end 194.183 105.4354) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_text "Cysat 1 SDR Breakout Board Cardedge Adapter \nC.S.B.B.C.A" (at 205.613 131.699 90) (layer F.SilkS))
  (gr_line (start 194.183 158.115) (end 194.183 105.537) (layer Edge.Cuts) (width 0.15))
  (zone (net 1) (net_name GND) (layer F.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 213.8426 158.0134) (xy 194.2846 158.0134) (xy 194.2846 105.6386) (xy 213.8426 105.6386)
      )
    )
  )
  (zone (net 2) (net_name +5V) (layer B.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 213.8426 158.0134) (xy 194.2846 158.0134) (xy 194.2846 105.6386) (xy 213.8426 105.6386)
      )
    )
  )
)
