Altium

Design Rule Verification Report

Date: 3/23/2019
Time: 7:26:59 PM
Elapsed Time: 00:00:01
Filename: C:\git\three\podiv-altium\src\prj\pcb\processor_pcb.PcbDoc
Warnings: 0
Rule Violations: 59

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=7mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=7mil) (Max=100mil) (Preferred=7mil) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=20mil) (Air Gap=10mil) (Entries=4) (All) 0
Acute Angle Constraint (Minimum=60.000) (All) 1
Hole Size Constraint (Min=1mil) (Max=200mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=8mil) (All),(All) 2
Silk To Solder Mask (Clearance=2mil) (IsPad),(All) 48
Silk to Silk (Clearance=3mil) (All),(All) 6
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) ((OnLayer('Bottom Overlay') OR OnLayer('top overlay'))) 0
Board Clearance Constraint (Gap=0mil) (All) 2
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 59

Acute Angle Constraint (Minimum=60.000) (All)
Acute Angle Constraint: (45.000 < 60.000) Between Polygon Region (62 hole(s)) Top Layer And Track (2438.757mil,5135mil)(2565mil,5135mil) on Top Layer (Angle = 45.000)
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Minimum Solder Mask Sliver (Gap=8mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (7.66mil < 8mil) Between Via (3020mil,5363.512mil) from Top Layer to Bottom Layer And Via (3020mil,5409.173mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [7.66mil] / [Bottom Solder] Mask Sliver [7.66mil]
Minimum Solder Mask Sliver Constraint: (2.827mil < 8mil) Between Via (3020mil,5409.173mil) from Top Layer to Bottom Layer And Via (3020mil,5450mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [2.827mil] / [Bottom Solder] Mask Sliver [2.827mil]
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Silk To Solder Mask (Clearance=2mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R28-1(3967mil,3638.374mil) on Top Layer And Track (3932mil,3613.374mil)(3932mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R28-1(3967mil,3638.374mil) on Top Layer And Track (3932mil,3613.374mil)(4002mil,3613.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R28-1(3967mil,3638.374mil) on Top Layer And Track (4002mil,3613.374mil)(4002mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R28-2(3967mil,3718.374mil) on Top Layer And Track (3932mil,3613.374mil)(3932mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R28-2(3967mil,3718.374mil) on Top Layer And Track (3932mil,3743.374mil)(4002mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R28-2(3967mil,3718.374mil) on Top Layer And Track (4002mil,3613.374mil)(4002mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R29-1(3887mil,3638.374mil) on Top Layer And Track (3852mil,3613.374mil)(3852mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R29-1(3887mil,3638.374mil) on Top Layer And Track (3852mil,3613.374mil)(3922mil,3613.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R29-1(3887mil,3638.374mil) on Top Layer And Track (3922mil,3613.374mil)(3922mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R29-2(3887mil,3718.374mil) on Top Layer And Track (3852mil,3613.374mil)(3852mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R29-2(3887mil,3718.374mil) on Top Layer And Track (3852mil,3743.374mil)(3922mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R29-2(3887mil,3718.374mil) on Top Layer And Track (3922mil,3613.374mil)(3922mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R30-1(3807mil,3638.374mil) on Top Layer And Track (3772mil,3613.374mil)(3772mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R30-1(3807mil,3638.374mil) on Top Layer And Track (3772mil,3613.374mil)(3842mil,3613.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R30-1(3807mil,3638.374mil) on Top Layer And Track (3842mil,3613.374mil)(3842mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R30-2(3807mil,3718.374mil) on Top Layer And Track (3772mil,3613.374mil)(3772mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R30-2(3807mil,3718.374mil) on Top Layer And Track (3772mil,3743.374mil)(3842mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R30-2(3807mil,3718.374mil) on Top Layer And Track (3842mil,3613.374mil)(3842mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R31-1(3727mil,3638.374mil) on Top Layer And Track (3692mil,3613.374mil)(3692mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R31-1(3727mil,3638.374mil) on Top Layer And Track (3692mil,3613.374mil)(3762mil,3613.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R31-1(3727mil,3638.374mil) on Top Layer And Track (3762mil,3613.374mil)(3762mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R31-2(3727mil,3718.374mil) on Top Layer And Track (3692mil,3613.374mil)(3692mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R31-2(3727mil,3718.374mil) on Top Layer And Track (3692mil,3743.374mil)(3762mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R31-2(3727mil,3718.374mil) on Top Layer And Track (3762mil,3613.374mil)(3762mil,3743.374mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R41-1(1254.252mil,3835.555mil) on Top Layer And Track (1149.252mil,3800.555mil)(1279.252mil,3800.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R41-1(1254.252mil,3835.555mil) on Top Layer And Track (1149.252mil,3870.555mil)(1279.252mil,3870.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R41-1(1254.252mil,3835.555mil) on Top Layer And Track (1279.252mil,3800.555mil)(1279.252mil,3870.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R41-2(1174.252mil,3835.555mil) on Top Layer And Track (1149.252mil,3800.555mil)(1149.252mil,3870.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R41-2(1174.252mil,3835.555mil) on Top Layer And Track (1149.252mil,3800.555mil)(1279.252mil,3800.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R41-2(1174.252mil,3835.555mil) on Top Layer And Track (1149.252mil,3870.555mil)(1279.252mil,3870.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R42-1(1254.252mil,3935.555mil) on Top Layer And Track (1149.252mil,3900.555mil)(1279.252mil,3900.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R42-1(1254.252mil,3935.555mil) on Top Layer And Track (1149.252mil,3970.555mil)(1279.252mil,3970.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R42-1(1254.252mil,3935.555mil) on Top Layer And Track (1279.252mil,3900.555mil)(1279.252mil,3970.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R42-2(1174.252mil,3935.555mil) on Top Layer And Track (1149.252mil,3900.555mil)(1149.252mil,3970.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R42-2(1174.252mil,3935.555mil) on Top Layer And Track (1149.252mil,3900.555mil)(1279.252mil,3900.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R42-2(1174.252mil,3935.555mil) on Top Layer And Track (1149.252mil,3970.555mil)(1279.252mil,3970.555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R7-1(3097.5mil,5559.173mil) on Top Layer And Track (3062.5mil,5514.173mil)(3062.5mil,5604.173mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R7-1(3097.5mil,5559.173mil) on Top Layer And Track (3062.5mil,5514.173mil)(3242.5mil,5514.173mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R7-1(3097.5mil,5559.173mil) on Top Layer And Track (3062.5mil,5604.173mil)(3242.5mil,5604.173mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R7-2(3207.5mil,5559.173mil) on Top Layer And Track (3062.5mil,5514.173mil)(3242.5mil,5514.173mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R7-2(3207.5mil,5559.173mil) on Top Layer And Track (3062.5mil,5604.173mil)(3242.5mil,5604.173mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R7-2(3207.5mil,5559.173mil) on Top Layer And Track (3242.5mil,5514.173mil)(3242.5mil,5604.173mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R8-1(3210mil,5406.693mil) on Top Layer And Track (3065mil,5361.693mil)(3245mil,5361.693mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R8-1(3210mil,5406.693mil) on Top Layer And Track (3065mil,5451.693mil)(3245mil,5451.693mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R8-1(3210mil,5406.693mil) on Top Layer And Track (3245mil,5361.693mil)(3245mil,5451.693mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R8-2(3100mil,5406.693mil) on Top Layer And Track (3065mil,5361.693mil)(3065mil,5451.693mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R8-2(3100mil,5406.693mil) on Top Layer And Track (3065mil,5361.693mil)(3245mil,5361.693mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
Silk To Solder Mask Clearance Constraint: (1mil < 2mil) Between Pad R8-2(3100mil,5406.693mil) on Top Layer And Track (3065mil,5451.693mil)(3245mil,5451.693mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1mil]
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Silk to Silk (Clearance=3mil) (All),(All)
Silk To Silk Clearance Constraint: (Collision < 3mil) Between Text "1" (1404.882mil,4922.52mil) on Top Overlay And Track (1400mil,3398.977mil)(1400mil,5703.977mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Silk To Silk Clearance Constraint: (2.892mil < 3mil) Between Text "45" (1560mil,3355mil) on Top Overlay And Track (1400mil,3398.977mil)(1600mil,3398.977mil) on Top Overlay Silk Text to Silk Clearance [2.892mil]
Silk To Silk Clearance Constraint: (2.94mil < 3mil) Between Text "LED4" (3843.114mil,3886.187mil) on Top Overlay And Text "LED5" (3755mil,3886.187mil) on Top Overlay Silk Text to Silk Clearance [2.94mil]
Silk To Silk Clearance Constraint: (Collision < 3mil) Between Text "P2" (1358.414mil,4375.213mil) on Top Overlay And Track (1400mil,3398.977mil)(1400mil,5703.977mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Silk To Silk Clearance Constraint: (Collision < 3mil) Between Text "R3" (4320mil,5430mil) on Top Overlay And Track (4318.701mil,5341.102mil)(4318.701mil,5411.968mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Silk To Silk Clearance Constraint: (2.927mil < 3mil) Between Text "R3" (4320mil,5430mil) on Top Overlay And Track (4350.257mil,5344.567mil)(4350.257mil,5415.433mil) on Top Overlay Silk Text to Silk Clearance [2.927mil]
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Board Clearance Constraint (Gap=0mil) (All)
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text ".Layer_Name" (1586.843mil,2795mil) on Bottom Layer
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text ".Layer_Name" (1586.843mil,2795mil) on Top Layer
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