(kicad_pcb (version 20171130) (host pcbnew 5.1.2-f72e74a~84~ubuntu19.04.1) (general (thickness 1.6) (drawings 5) (tracks 0) (zones 0) (modules 1) (nets 1) ) (page USLetter) (title_block (title "Project Title") ) (layers (0 F.Cu signal) (31 B.Cu signal) (34 B.Paste user hide) (35 F.Paste user hide) (36 B.SilkS user hide) (37 F.SilkS user hide) (38 B.Mask user) (39 F.Mask user hide) (40 Dwgs.User user hide) (44 Edge.Cuts user) (46 B.CrtYd user hide) (47 F.CrtYd user hide) (48 B.Fab user hide) (49 F.Fab user hide) ) (setup (last_trace_width 0.254) (user_trace_width 0.1524) (user_trace_width 0.254) (user_trace_width 0.3302) (user_trace_width 0.508) (user_trace_width 0.762) (user_trace_width 1.27) (trace_clearance 0.254) (zone_clearance 0.508) (zone_45_only no) (trace_min 0.1524) (via_size 0.6858) (via_drill 0.3302) (via_min_size 0.6858) (via_min_drill 0.3302) (user_via 0.6858 0.3302) (user_via 0.762 0.4064) (user_via 0.8636 0.508) (uvia_size 0.6858) (uvia_drill 0.3302) (uvias_allowed no) (uvia_min_size 0) (uvia_min_drill 0) (edge_width 0.1524) (segment_width 0.1524) (pcb_text_width 0.1524) (pcb_text_size 1.016 1.016) (mod_edge_width 0.1524) (mod_text_size 1.016 1.016) (mod_text_width 0.1524) (pad_size 6.985 1.016) (pad_drill 0) (pad_to_mask_clearance 0.0762) (solder_mask_min_width 0.1016) (pad_to_paste_clearance -0.0762) (aux_axis_origin 0 0) (visible_elements FFFEDF7D) (pcbplotparams (layerselection 0x310fc_80000001) (usegerberextensions true) (usegerberattributes false) (usegerberadvancedattributes false) (creategerberjobfile false) (excludeedgelayer true) (linewidth 0.100000) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 0) (scaleselection 1) (outputdirectory "gerbers")) ) (net 0 "") (net_class Default "This is the default net class." (clearance 0.254) (trace_width 0.254) (via_dia 0.6858) (via_drill 0.3302) (uvia_dia 0.6858) (uvia_drill 0.3302) ) (module Wire_Pads:0.1in_40_card_edge (layer F.Cu) (tedit 5D218F67) (tstamp 5CF49AD5) (at 137.4648 78.486) (tags "card edge ") (solder_mask_margin -0.000254) (attr smd) (fp_text reference "" (at 0 0 -90) (layer F.SilkS) hide (effects (font (size 0.0254 0.0254) (thickness 0.000001))) ) (fp_text value "" (at 0 0) (layer F.Fab) hide (effects (font (size 0.0254 0.0254) (thickness 0.000001))) ) (pad 1 smd rect (at 0 0) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 1 smd rect (at 0 0) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 2 smd rect (at 0 2.54) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 3 smd rect (at 0 5.08) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 4 smd rect (at 0 7.62) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 5 smd rect (at 0 10.16) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 6 smd rect (at 0 12.7) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 7 smd rect (at 0 15.24) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 8 smd rect (at 0 17.78) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 9 smd rect (at 0 20.32) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 10 smd rect (at 0 22.86) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 11 smd rect (at 0 25.4) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 12 smd rect (at 0 27.94) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 13 smd rect (at 0 30.48) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 14 smd rect (at 0 33.02) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 15 smd rect (at 0 35.56) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 16 smd rect (at 0 38.1) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 17 smd rect (at 0 40.64) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 18 smd rect (at 0 43.18) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 19 smd rect (at 0 45.72) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 20 smd rect (at 0 48.26) (size 6.985 1.016) (layers F.Cu F.Mask)) (pad 2 smd rect (at 0 2.54) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 3 smd rect (at 0 5.08) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 4 smd rect (at 0 7.62) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 5 smd rect (at 0 10.16) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 6 smd rect (at 0 12.7) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 7 smd rect (at 0 15.24) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 8 smd rect (at 0 17.78) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 9 smd rect (at 0 20.32) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 10 smd rect (at 0 22.86) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 11 smd rect (at 0 25.4) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 12 smd rect (at 0 27.94) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 13 smd rect (at 0 30.48) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 14 smd rect (at 0 33.02) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 15 smd rect (at 0 35.56) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 16 smd rect (at 0 38.1) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 17 smd rect (at 0 40.64) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 18 smd rect (at 0 43.18) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 19 smd rect (at 0 45.72) (size 6.985 1.016) (layers B.Cu B.Mask)) (pad 20 smd rect (at 0 48.26) (size 6.985 1.016) (layers B.Cu B.Mask)) ) (gr_line (start 133.9596 77.216) (end 140.97 77.216) (layer Edge.Cuts) (width 0.1524) (tstamp 5D218C88)) (gr_line (start 133.9596 128.016) (end 140.97 128.016) (layer Edge.Cuts) (width 0.1524) (tstamp 5D218C79)) (gr_line (start 140.97 128.016) (end 140.97 77.216) (layer Edge.Cuts) (width 0.1524) (tstamp 5D218C43)) (gr_line (start 133.9596 77.216) (end 133.9596 128.016) (layer Edge.Cuts) (width 0.1524)) (gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. BOARDS SHALL BE ROHS COMPLIANT. \n5. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n MINIMUM SPACE - 0.006 INCH.\n MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User) (effects (font (size 2.54 2.54) (thickness 0.254)) (justify left)) ) )