(kicad_pcb (version 20171130) (host pcbnew 5.1.12-84ad8e8a86~92~ubuntu20.04.1)
  (general
    (thickness 1.6)
    (drawings 18)
    (tracks 34)
    (zones 0)
    (modules 3)
    (nets 6)
  )
  (page USLetter)
  (title_block
    (title "External Clock Interface for RT-SDR V3")
    (date 2021-03-13)
    (rev -)
    (company "Amateur Radio / Phased Arrays")
    (comment 2 creativecommons.org/licenses/by/4.0/)
    (comment 3 "License: CC BY 4.0")
    (comment 4 "Author: Zach Leffke, KJ4QLP")
  )
  (layers
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    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
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    (user_trace_width 0.254)
    (user_trace_width 0.508)
    (user_trace_width 0.762)
    (user_trace_width 1.016)
    (trace_clearance 0.1524)
    (zone_clearance 0.1524)
    (zone_45_only no)
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    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
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    (pad_drill 0.762)
    (pad_to_mask_clearance 0)
    (aux_axis_origin 0 0)
    (visible_elements FFFDFF7F)
    (pcbplotparams
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      (usegerberextensions false)
      (usegerberattributes true)
      (usegerberadvancedattributes true)
      (creategerberjobfile true)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
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      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
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      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 GND)
  (net 2 /SCLK)
  (net 3 /SDAT)
  (net 4 /CLK)
  (net 5 /3V3)
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    (uvia_dia 0.3)
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    (diff_pair_width 0.254)
    (diff_pair_gap 0.254)
    (add_net /3V3)
    (add_net /CLK)
    (add_net /SCLK)
    (add_net /SDAT)
    (add_net GND)
  )
  (module Connector_PinHeader_2.00mm:PinHeader_1x07_P2.00mm_Vertical (layer B.Cu) (tedit 59FED667)
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    (descr "Through hole straight pin header, 1x07, 2.00mm pitch, single row")
    (tags "Through hole pin header THT 1x07 2.00mm single row")
    (fp_text reference J1 (at 0 1.62 90) (layer B.SilkS))
    (fp_text value Conn_01x07_Male (at 0 -14.06 270) (layer B.Fab))
    (fp_text user %R (at 0 -6) (layer B.Fab))
    (pad 7 thru_hole oval (at 0 -12 90) (size 1.35 1.35) (drill 0.8) (layers *.Cu *.Mask)
      (net 2 /SCLK))
    (pad 6 thru_hole oval (at 0 -10 90) (size 1.35 1.35) (drill 0.8) (layers *.Cu *.Mask)
      (net 3 /SDAT))
    (pad 5 thru_hole oval (at 0 -8 90) (size 1.35 1.35) (drill 0.8) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 4 thru_hole oval (at 0 -6 90) (size 1.35 1.35) (drill 0.8) (layers *.Cu *.Mask)
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    (pad 3 thru_hole oval (at 0 -4 90) (size 1.35 1.35) (drill 0.8) (layers *.Cu *.Mask)
      (net 4 /CLK))
    (pad 2 thru_hole oval (at 0 -2 90) (size 1.35 1.35) (drill 0.8) (layers *.Cu *.Mask)
      (net 5 /3V3))
    (pad 1 thru_hole rect (at 0 0 90) (size 1.35 1.35) (drill 0.8) (layers *.Cu *.Mask)
      (net 1 GND))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.00mm.3dshapes/PinHeader_1x07_P2.00mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module digikey-footprints:Molex_734120114_UMC_RF_CONN_Vertical (layer F.Cu) (tedit 5D2892B1)
    (at 148.59 104.775 90)
    (attr smd)
    (fp_text reference J3 (at -1.905 1.905) (layer F.SilkS))
    (fp_text value 0734120114 (at 0.2 3.175 -90) (layer F.Fab))
    (fp_text user %R (at -0.635 -0.635 -90) (layer F.Fab))
    (pad 1 smd rect (at -1.5 0 90) (size 1 2.2) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 1 smd rect (at 1.5 0 90) (size 1 2.2) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 2 smd rect (at 0 1.5 90) (size 1 1) (layers F.Cu F.Paste F.Mask)
      (net 4 /CLK))
    (pad 1 smd rect (at 0 -1.5 90) (size 1 1) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
  )
  (module digikey-footprints:Molex_734120114_UMC_RF_CONN_Vertical (layer F.Cu) (tedit 5D2892B1)
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    (attr smd)
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    (fp_text value 0734120114 (at 0.2 3.175 90) (layer F.Fab))
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      (net 1 GND))
    (pad 1 smd rect (at 1.5 0 270) (size 1 2.2) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 2 smd rect (at 0 1.5 270) (size 1 1) (layers F.Cu F.Paste F.Mask)
      (net 4 /CLK))
    (pad 1 smd rect (at 0 -1.5 270) (size 1 1) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
  )
  (gr_text 7 (at 152.654 102.87) (layer F.SilkS))
  (gr_text USB<--->SMA (at 158.75 102.87) (layer F.SilkS))
  (gr_text 1 (at 164.846 102.87) (layer F.SilkS))
  (gr_text SDAT (at 152.654 106.68 270) (layer F.SilkS))
  (gr_text SCLK (at 154.686 106.68 270) (layer F.SilkS))
  (gr_text GND (at 156.718 106.68 270) (layer F.SilkS))
  (gr_text GND (at 164.846 106.68 270) (layer F.SilkS))
  (gr_text 3V3 (at 162.814 106.68 270) (layer F.SilkS))
  (gr_text CLK (at 158.75 106.68 270) (layer F.SilkS))
  (gr_text CLK (at 160.782 106.68 270) (layer F.SilkS))
  (gr_text SN: (at 149.86 104.14) (layer B.SilkS))
  (gr_text "RTL-SDRv3 CLOCK INTERFACE, V2, REV-" (at 170.815 102.87) (layer B.SilkS))
  (gr_line (start 171.45 107.95) (end 171.45 101.6) (layer Edge.Cuts) (width 0.05))
  (gr_text "Z. LEFFKE, VT-NSI, 20220209" (at 170.815 106.68) (layer B.SilkS))
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  (gr_line (start 146.05 107.95) (end 171.45 107.95) (layer Edge.Cuts) (width 0.05))
  (zone (net 1) (net_name GND) (layer F.Cu) (hatch edge 0.508)
    (connect_pads yes (clearance 0.1524))
    (min_thickness 0.1524)
    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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      )
    )
  )
  (zone (net 1) (net_name GND) (layer B.Cu) (hatch edge 0.508)
    (connect_pads yes (clearance 0.1524))
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