(kicad_pcb (version 20171130) (host pcbnew "(5.1.0)-1")
  (general
    (thickness 1.6)
    (drawings 15)
    (tracks 30)
    (zones 0)
    (modules 7)
    (nets 9)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.254)
    (user_trace_width 0.1524)
    (user_trace_width 0.254)
    (trace_clearance 0.1524)
    (zone_clearance 0.1524)
    (zone_45_only no)
    (trace_min 0.1524)
    (via_size 0.508)
    (via_drill 0.254)
    (via_min_size 0.508)
    (via_min_drill 0.254)
    (user_via 0.508 0.254)
    (user_via 0.762 0.3048)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0)
    (solder_mask_min_width 0.1524)
    (aux_axis_origin 0 0)
    (visible_elements FFFDFF7F)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.152400)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 GND)
  (net 2 "Net-(C1-Pad1)")
  (net 3 "Net-(C2-Pad1)")
  (net 4 "Net-(D1-Pad2)")
  (net 5 "Net-(D1-Pad1)")
  (net 6 Out)
  (net 7 +12V)
  (net 8 "Net-(POT1-Pad2)")
  (net_class Default "This is the default net class."
    (clearance 0.1524)
    (trace_width 0.1524)
    (via_dia 0.508)
    (via_drill 0.254)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(C1-Pad1)")
    (add_net "Net-(C2-Pad1)")
    (add_net "Net-(D1-Pad1)")
    (add_net "Net-(D1-Pad2)")
    (add_net "Net-(POT1-Pad2)")
    (add_net Out)
  )
  (net_class Pwr ""
    (clearance 0.1524)
    (trace_width 0.254)
    (via_dia 0.762)
    (via_drill 0.3048)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net +12V)
    (add_net GND)
  )
  (module Connector_Wire:SolderWirePad_1x03_P4.445mm_Drill1.5mm (layer F.Cu) (tedit 5AEE5F77)
    (at 143.51 45.847)
    (descr "Wire solder connection")
    (tags connector)
    (attr virtual)
    (fp_text reference POT1 (at 4.445 -3.81) (layer F.SilkS) hide)
    (fp_text value 5K (at 4.445 3.81) (layer F.Fab))
    (fp_text user %R (at 4.445 0) (layer F.Fab))
    (pad 3 thru_hole circle (at 8.89 0) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 5 "Net-(D1-Pad1)"))
    (pad 2 thru_hole circle (at 4.445 0) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 8 "Net-(POT1-Pad2)"))
    (pad 1 thru_hole rect (at 0 0) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 4 "Net-(D1-Pad2)"))
  )
  (module Connector_Wire:SolderWirePad_1x02_P5.08mm_Drill1.5mm (layer F.Cu) (tedit 5AEE5F19)
    (at 148.59 55.88 180)
    (descr "Wire solder connection")
    (tags connector)
    (attr virtual)
    (fp_text reference J2 (at 2.54 -3.81 180) (layer F.SilkS) hide)
    (fp_text value Conn_01x02 (at 2.54 3.81 180) (layer F.Fab))
    (fp_text user %R (at 2.54 0 180) (layer F.Fab))
    (pad 2 thru_hole circle (at 5.08 0 180) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 1 thru_hole rect (at 0 0 180) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 7 +12V))
  )
  (module Connector_Wire:SolderWirePad_1x03_P4.445mm_Drill1.5mm (layer F.Cu) (tedit 5AEE5F77)
    (at 156.972 45.847 270)
    (descr "Wire solder connection")
    (tags connector)
    (attr virtual)
    (fp_text reference J1 (at 4.445 -3.81 270) (layer F.SilkS) hide)
    (fp_text value Conn_01x03 (at 4.445 3.81 270) (layer F.Fab))
    (fp_text user %R (at 4.445 0 270) (layer F.Fab))
    (pad 3 thru_hole circle (at 8.89 0 270) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 2 thru_hole circle (at 4.445 0 270) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 6 Out))
    (pad 1 thru_hole rect (at 0 0 270) (size 3.50012 3.50012) (drill 1.50114) (layers *.Cu *.Mask)
      (net 7 +12V))
  )
  (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5A02F2D3)
    (at 150.876 50.927)
    (descr "8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf)")
    (tags "SOIC 1.27")
    (attr smd)
    (fp_text reference U1 (at 1.016 3.429 180) (layer F.SilkS))
    (fp_text value NE555 (at 0 3.5) (layer F.Fab))
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 8 smd rect (at 2.7 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 7 +12V))
    (pad 7 smd rect (at 2.7 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 6 Out))
    (pad 6 smd rect (at 2.7 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(C1-Pad1)"))
    (pad 5 smd rect (at 2.7 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(C2-Pad1)"))
    (pad 4 smd rect (at -2.7 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 7 +12V))
    (pad 3 smd rect (at -2.7 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 8 "Net-(POT1-Pad2)"))
    (pad 2 smd rect (at -2.7 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(C1-Pad1)"))
    (pad 1 smd rect (at -2.7 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Package_TO_SOT_SMD:SOT-23 (layer F.Cu) (tedit 5A02FF57)
    (at 143.129 49.911 270)
    (descr "SOT-23, Standard")
    (tags SOT-23)
    (attr smd)
    (fp_text reference D1 (at 2.413 -0.0635) (layer F.SilkS))
    (fp_text value MMBD7000LT1G (at 0 2.5 270) (layer F.Fab))
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 3 smd rect (at 1 0 270) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(C1-Pad1)"))
    (pad 2 smd rect (at -1 0.95 270) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
      (net 4 "Net-(D1-Pad2)"))
    (pad 1 smd rect (at -1 -0.95 270) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
      (net 5 "Net-(D1-Pad1)"))
    (model ${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-23.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5B301BBE)
    (at 153.543 55.245 270)
    (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
    (tags capacitor)
    (attr smd)
    (fp_text reference C2 (at 2.159 0) (layer F.SilkS))
    (fp_text value 1uF (at 0 1.43 270) (layer F.Fab))
    (fp_text user %R (at 0 0 270) (layer F.Fab))
    (pad 2 smd roundrect (at 0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 GND))
    (pad 1 smd roundrect (at -0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 3 "Net-(C2-Pad1)"))
    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5B301BBE)
    (at 145.796 49.657 90)
    (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
    (tags capacitor)
    (attr smd)
    (fp_text reference C1 (at -2.413 -0.127 90) (layer F.SilkS))
    (fp_text value 1uF (at 0 1.43 90) (layer F.Fab))
    (fp_text user %R (at 0 0 90) (layer F.Fab))
    (pad 2 smd roundrect (at 0.7875 0 90) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 GND))
    (pad 1 smd roundrect (at -0.7875 0 90) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 2 "Net-(C1-Pad1)"))
    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_text "PWM \nConroller V1" (at 141.4145 49.9745 180) (layer B.SilkS))
  (gr_text + (at 155.3845 48.26) (layer F.SilkS))
  (gr_text - (at 155.067 56.388 90) (layer F.SilkS))
  (gr_text - (at 141.859 54.102) (layer F.SilkS))
  (gr_text + (at 145.9865 54.102) (layer F.SilkS))
  (gr_line (start 141.224 58.166) (end 141.224 43.561) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 159.258 58.166) (end 141.224 58.166) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 159.258 43.561) (end 159.258 58.166) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 141.224 43.561) (end 159.258 43.561) (layer Edge.Cuts) (width 0.05))
  (zone (net 1) (net_name GND) (layer F.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.1524))
    (min_thickness 0.1524)
    (fill yes (arc_segments 32) (thermal_gap 0.1524) (thermal_bridge_width 0.889))
    (polygon
      (pts
        (xy 141.224 43.561) (xy 159.258 43.561) (xy 159.258 58.166) (xy 141.224 58.166)
      )
    )
  )
  (zone (net 7) (net_name +12V) (layer B.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.1524))
    (min_thickness 0.1524)
    (fill yes (arc_segments 32) (thermal_gap 0.1524) (thermal_bridge_width 0.889))
    (polygon
      (pts
        (xy 141.224 43.561) (xy 159.258 43.561) (xy 159.258 58.166) (xy 141.224 58.166)
      )
    )
  )
)
