(kicad_pcb (version 20171130) (host pcbnew "(5.1.8)-1")
  (general
    (thickness 1.6)
    (drawings 22)
    (tracks 55)
    (zones 0)
    (modules 9)
    (nets 36)
  )
  (page A4)
  (title_block
    (title "Raspberry Pi Zero W Mains Power HAT")
    (date 2020-11-09)
    (rev 1.0)
    (comment 1 "This PCB design is licensed under MIT Open Source License.")
    (comment 2 "Based on Raspberry Pi Zero (W) uHAT Template Board")
  )
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user hide)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user hide)
    (49 F.Fab user hide)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (via_size 0.8)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.15)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.051)
    (solder_mask_min_width 0.25)
    (aux_axis_origin 0 0)
    (grid_origin 121.032 94.568)
    (visible_elements 7FFFFFFF)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 +3V3)
  (net 2 +5V)
  (net 3 /GPIO2_SDA1)
  (net 4 /GPIO3_SCL1)
  (net 5 GND)
  (net 6 /GPIO4_GPIO_GCLK)
  (net 7 /GPIO14_TXD0)
  (net 8 /GPIO15_RXD0)
  (net 9 /GPIO17_GEN0)
  (net 10 /GPIO18_GEN1)
  (net 11 /GPIO27_GEN2)
  (net 12 /GPIO22_GEN3)
  (net 13 /GPIO23_GEN4)
  (net 14 /GPIO24_GEN5)
  (net 15 /GPIO10_SPI_MOSI)
  (net 16 /GPIO9_SPI_MISO)
  (net 17 /GPIO25_GEN6)
  (net 18 /GPIO11_SPI_SCLK)
  (net 19 /GPIO8_SPI_CE0_N)
  (net 20 /GPIO7_SPI_CE1_N)
  (net 21 /ID_SD)
  (net 22 /ID_SC)
  (net 23 /GPIO5)
  (net 24 /GPIO6)
  (net 25 /GPIO12)
  (net 26 /GPIO13)
  (net 27 /GPIO19)
  (net 28 /GPIO16)
  (net 29 /GPIO26)
  (net 30 /GPIO20)
  (net 31 /GPIO21)
  (net 32 "Net-(PS1-Pad5)")
  (net 33 "Net-(J2-Pad1)")
  (net 34 "Net-(J2-Pad2)")
  (net 35 "Net-(PS2-Pad5)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.8)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net +3V3)
    (add_net +5V)
    (add_net /GPIO10_SPI_MOSI)
    (add_net /GPIO11_SPI_SCLK)
    (add_net /GPIO12)
    (add_net /GPIO13)
    (add_net /GPIO14_TXD0)
    (add_net /GPIO15_RXD0)
    (add_net /GPIO16)
    (add_net /GPIO17_GEN0)
    (add_net /GPIO18_GEN1)
    (add_net /GPIO19)
    (add_net /GPIO20)
    (add_net /GPIO21)
    (add_net /GPIO22_GEN3)
    (add_net /GPIO23_GEN4)
    (add_net /GPIO24_GEN5)
    (add_net /GPIO25_GEN6)
    (add_net /GPIO26)
    (add_net /GPIO27_GEN2)
    (add_net /GPIO2_SDA1)
    (add_net /GPIO3_SCL1)
    (add_net /GPIO4_GPIO_GCLK)
    (add_net /GPIO5)
    (add_net /GPIO6)
    (add_net /GPIO7_SPI_CE1_N)
    (add_net /GPIO8_SPI_CE0_N)
    (add_net /GPIO9_SPI_MISO)
    (add_net /ID_SC)
    (add_net /ID_SD)
    (add_net GND)
    (add_net "Net-(J2-Pad1)")
    (add_net "Net-(J2-Pad2)")
    (add_net "Net-(PS1-Pad5)")
    (add_net "Net-(PS2-Pad5)")
  )
  (module Connector_PinHeader_2.54mm:PinHeader_2x04_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC)
    (at 178.182 103.458)
    (descr "Through hole straight pin header, 2x04, 2.54mm pitch, double rows")
    (tags "Through hole pin header THT 2x04 2.54mm double row")
    (fp_text reference J3 (at 1.27 -2.33) (layer F.SilkS))
    (fp_text value "SPI Breakout" (at 1.27 9.95) (layer F.Fab))
    (fp_text user %R (at 1.27 3.81 90) (layer F.Fab))
    (pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 15 /GPIO10_SPI_MOSI))
    (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 17 /GPIO25_GEN6))
    (pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 16 /GPIO9_SPI_MISO))
    (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 19 /GPIO8_SPI_CE0_N))
    (pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 18 /GPIO11_SPI_SCLK))
    (pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 +5V))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 +3V3))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x04_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Converter_ACDC:Converter_ACDC_MeanWell_IRM-03-xx_THT (layer B.Cu) (tedit 5C747753)
    (at 165.482 117.428 90)
    (descr "ACDC-Converter, 3W, Meanwell, IRM-03, THT, https://www.meanwell.com/Upload/PDF/IRM-03/IRM-03-SPEC.PDF")
    (tags "ACDC-Converter 3W THT")
    (fp_text reference PS2 (at 8.89 4.5 90) (layer B.SilkS))
    (fp_text value IRM-03-5 (at 8.89 -16.24 90) (layer B.Fab))
    (fp_text user %R (at 8.89 -14.24 90) (layer B.Fab))
    (pad 5 thru_hole circle (at 0 -30.48 90) (size 2.3 2.3) (drill 0.76) (layers *.Cu *.Mask)
      (net 35 "Net-(PS2-Pad5)"))
    (pad 1 thru_hole rect (at 0 0 90) (size 2.3 2) (drill 0.8) (layers *.Cu *.Mask)
      (net 33 "Net-(J2-Pad1)"))
    (pad 3 thru_hole circle (at 0 -5.08 90) (size 2.3 2.3) (drill 0.8) (layers *.Cu *.Mask)
      (net 34 "Net-(J2-Pad2)"))
    (pad 14 thru_hole circle (at 17.78 -30.48 90) (size 2.3 2.3) (drill 0.76) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 16 thru_hole circle (at 17.78 -25.4 90) (size 2.3 2.3) (drill 0.76) (layers *.Cu *.Mask)
      (net 2 +5V))
    (model ${KISYS3DMOD}/Converter_ACDC.3dshapes/Converter_ACDC_MeanWell_IRM-03-xx_THT.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Converter_ACDC:Converter_ACDC_MeanWell_IRM-03-xx_THT (layer F.Cu) (tedit 5C747753)
    (at 141.352 117.428 90)
    (descr "ACDC-Converter, 3W, Meanwell, IRM-03, THT, https://www.meanwell.com/Upload/PDF/IRM-03/IRM-03-SPEC.PDF")
    (tags "ACDC-Converter 3W THT")
    (fp_text reference PS1 (at 8.89 -4.5 90) (layer F.SilkS))
    (fp_text value IRM-03-5 (at 8.89 16.24 90) (layer F.Fab))
    (fp_text user %R (at 8.89 14.24 90) (layer F.Fab))
    (pad 5 thru_hole circle (at 0 30.48 90) (size 2.3 2.3) (drill 0.76) (layers *.Cu *.Mask)
      (net 32 "Net-(PS1-Pad5)"))
    (pad 1 thru_hole rect (at 0 0 90) (size 2.3 2) (drill 0.8) (layers *.Cu *.Mask)
      (net 33 "Net-(J2-Pad1)"))
    (pad 3 thru_hole circle (at 0 5.08 90) (size 2.3 2.3) (drill 0.8) (layers *.Cu *.Mask)
      (net 34 "Net-(J2-Pad2)"))
    (pad 14 thru_hole circle (at 17.78 30.48 90) (size 2.3 2.3) (drill 0.76) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 16 thru_hole circle (at 17.78 25.4 90) (size 2.3 2.3) (drill 0.76) (layers *.Cu *.Mask)
      (net 2 +5V))
    (model ${KISYS3DMOD}/Converter_ACDC.3dshapes/Converter_ACDC_MeanWell_IRM-03-xx_THT.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module lib:PinSocket_2x20_P2.54mm_Vertical_Centered_Anchor (layer B.Cu) (tedit 5C78E1B8)
    (at 125.902 95.838 270)
    (descr "Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated")
    (tags "Through hole socket strip THT 2x20 2.54mm double row")
    (fp_text reference J1 (at 2.54 1.06) (layer B.SilkS))
    (fp_text value GPIO_CONNECTOR (at 2.7 -27.3) (layer B.Fab))
    (fp_text user %R (at 2.8 -18.3 180) (layer B.Fab))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 +3V3))
    (pad 2 thru_hole oval (at -2.54 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 +5V))
    (pad 3 thru_hole oval (at 0 -2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 /GPIO2_SDA1))
    (pad 4 thru_hole oval (at -2.54 -2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 +5V))
    (pad 5 thru_hole oval (at 0 -5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 /GPIO3_SCL1))
    (pad 6 thru_hole oval (at -2.54 -5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 7 thru_hole oval (at 0 -7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 /GPIO4_GPIO_GCLK))
    (pad 8 thru_hole oval (at -2.54 -7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 7 /GPIO14_TXD0))
    (pad 9 thru_hole oval (at 0 -10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 10 thru_hole oval (at -2.54 -10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 8 /GPIO15_RXD0))
    (pad 11 thru_hole oval (at 0 -12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 9 /GPIO17_GEN0))
    (pad 12 thru_hole oval (at -2.54 -12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 10 /GPIO18_GEN1))
    (pad 13 thru_hole oval (at 0 -15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 11 /GPIO27_GEN2))
    (pad 14 thru_hole oval (at -2.54 -15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 15 thru_hole oval (at 0 -17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 12 /GPIO22_GEN3))
    (pad 16 thru_hole oval (at -2.54 -17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 13 /GPIO23_GEN4))
    (pad 17 thru_hole oval (at 0 -20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 +3V3))
    (pad 18 thru_hole oval (at -2.54 -20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 14 /GPIO24_GEN5))
    (pad 19 thru_hole oval (at 0 -22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 15 /GPIO10_SPI_MOSI))
    (pad 20 thru_hole oval (at -2.54 -22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 21 thru_hole oval (at 0 -25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 16 /GPIO9_SPI_MISO))
    (pad 22 thru_hole oval (at -2.54 -25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 17 /GPIO25_GEN6))
    (pad 23 thru_hole oval (at 0 -27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 18 /GPIO11_SPI_SCLK))
    (pad 24 thru_hole oval (at -2.54 -27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 19 /GPIO8_SPI_CE0_N))
    (pad 25 thru_hole oval (at 0 -30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 26 thru_hole oval (at -2.54 -30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 20 /GPIO7_SPI_CE1_N))
    (pad 27 thru_hole oval (at 0 -33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 21 /ID_SD))
    (pad 28 thru_hole oval (at -2.54 -33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 22 /ID_SC))
    (pad 29 thru_hole oval (at 0 -35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 23 /GPIO5))
    (pad 30 thru_hole oval (at -2.54 -35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 31 thru_hole oval (at 0 -38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 24 /GPIO6))
    (pad 32 thru_hole oval (at -2.54 -38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 25 /GPIO12))
    (pad 33 thru_hole oval (at 0 -40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 26 /GPIO13))
    (pad 34 thru_hole oval (at -2.54 -40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 35 thru_hole oval (at 0 -43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 27 /GPIO19))
    (pad 36 thru_hole oval (at -2.54 -43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 28 /GPIO16))
    (pad 37 thru_hole oval (at 0 -45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 29 /GPIO26))
    (pad 38 thru_hole oval (at -2.54 -45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 30 /GPIO20))
    (pad 39 thru_hole oval (at 0 -48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 GND))
    (pad 40 thru_hole oval (at -2.54 -48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 31 /GPIO21))
    (model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_2x20_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module lib:MountingHole_2.7mm_M2.5_uHAT_RPi locked (layer F.Cu) (tedit 5C78B840)
    (at 121.032 94.568)
    (descr "Mounting Hole 2.7mm, no annular, M2.5")
    (tags "mounting hole 2.7mm no annular m2.5")
    (attr virtual)
    (fp_text reference H1 (at 0 -3.7) (layer F.SilkS) hide)
    (fp_text value MountingHole (at 0 3.7) (layer F.Fab) hide)
    (fp_text user %R (at 0.3 0) (layer F.Fab))
    (pad "" np_thru_hole circle (at 0 0) (size 2.7 2.7) (drill 2.7) (layers *.Cu *.Mask)
      (clearance 1.75))
  )
  (module lib:MountingHole_2.7mm_M2.5_uHAT_RPi locked (layer F.Cu) (tedit 5C78B867)
    (at 179.032 94.568)
    (descr "Mounting Hole 2.7mm, no annular, M2.5")
    (tags "mounting hole 2.7mm no annular m2.5")
    (attr virtual)
    (fp_text reference H2 (at 0 -3.7) (layer F.SilkS) hide)
    (fp_text value MountingHole (at 0 3.7) (layer F.Fab) hide)
    (fp_text user %R (at 0.3 0) (layer F.Fab))
    (pad "" np_thru_hole circle (at 0 0) (size 2.7 2.7) (drill 2.7) (layers *.Cu *.Mask)
      (clearance 1.75))
  )
  (module lib:MountingHole_2.7mm_M2.5_uHAT_RPi locked (layer F.Cu) (tedit 5C78B860)
    (at 179.032 117.568)
    (descr "Mounting Hole 2.7mm, no annular, M2.5")
    (tags "mounting hole 2.7mm no annular m2.5")
    (attr virtual)
    (fp_text reference H3 (at 0 -3.7) (layer F.SilkS) hide)
    (fp_text value MountingHole (at 0 3.7) (layer F.Fab) hide)
    (fp_text user %R (at 0.3 0) (layer F.Fab))
    (pad "" np_thru_hole circle (at 0 0) (size 2.7 2.7) (drill 2.7) (layers *.Cu *.Mask)
      (clearance 1.75))
  )
  (module lib:MountingHole_2.7mm_M2.5_uHAT_RPi locked (layer F.Cu) (tedit 5C78B845)
    (at 121.032 117.568)
    (descr "Mounting Hole 2.7mm, no annular, M2.5")
    (tags "mounting hole 2.7mm no annular m2.5")
    (attr virtual)
    (fp_text reference H4 (at 0 -3.7) (layer F.SilkS) hide)
    (fp_text value MountingHole (at 0 3.7) (layer F.Fab) hide)
    (fp_text user %R (at 0.3 0) (layer F.Fab))
    (pad "" np_thru_hole circle (at 0 0) (size 2.7 2.7) (drill 2.7) (layers *.Cu *.Mask)
      (clearance 1.75))
  )
  (module TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal (layer F.Cu) (tedit 5B294EE5)
    (at 123.572 103.458 270)
    (descr "Terminal Block Phoenix MKDS-1,5-2, 2 pins, pitch 5mm, size 10x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix")
    (tags "THT Terminal Block Phoenix MKDS-1,5-2 pitch 5mm size 10x9.8mm^2 drill 1.3mm pad 2.6mm")
    (fp_text reference J2 (at 2.5 -6.26 90) (layer F.SilkS))
    (fp_text value Screw_Terminal_01x02 (at 2.5 5.66 90) (layer F.Fab))
    (fp_text user %R (at 2.5 3.2 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0 270) (size 2.6 2.6) (drill 1.3) (layers *.Cu *.Mask)
      (net 33 "Net-(J2-Pad1)"))
    (pad 2 thru_hole circle (at 5 0 270) (size 2.6 2.6) (drill 1.3) (layers *.Cu *.Mask)
      (net 34 "Net-(J2-Pad2)"))
    (model ${KISYS3DMOD}/TerminalBlock_Phoenix.3dshapes/TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_text "Neutral\n" (at 126.112 112.348) (layer F.SilkS))
  (gr_text "Live\n" (at 127.382 99.648) (layer F.SilkS))
  (gr_text "Board dimensions are on Cmts (Comments) layer. \nDeselect it in Layers Manager to make them invisible.\n\nGPIO connector nets are not connected, these will get \nupdated as per your schematic/netlist." (at 120.524 139.272) (layer Cmts.User))
  (gr_text "Board Corner Radius = 3mm\nAll holes are M2.5" (at 184.278 87.202) (layer Cmts.User))
  (dimension 29 (width 0.3) (layer Cmts.User)
    (gr_text "29.000 mm" (at 135.532 103.868) (layer Cmts.User))
    (feature1 (pts (xy 121.032 94.568) (xy 121.032 102.354421)))
    (feature2 (pts (xy 150.032 94.568) (xy 150.032 102.354421)))
    (crossbar (pts (xy 150.032 101.768) (xy 121.032 101.768)))
    (arrow1a (pts (xy 121.032 101.768) (xy 122.158504 101.181579)))
    (arrow1b (pts (xy 121.032 101.768) (xy 122.158504 102.354421)))
    (arrow2a (pts (xy 150.032 101.768) (xy 148.905496 101.181579)))
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