(kicad_pcb (version 20171130) (host pcbnew 5.1.2-f72e74a~84~ubuntu18.04.1)
  (general
    (thickness 1.6)
    (drawings 4)
    (tracks 14)
    (zones 0)
    (modules 7)
    (nets 4)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.1524)
    (user_trace_width 0.1524)
    (user_trace_width 0.2)
    (user_trace_width 0.3)
    (user_trace_width 0.4)
    (user_trace_width 0.6)
    (user_trace_width 1)
    (user_trace_width 1.5)
    (user_trace_width 2)
    (trace_clearance 0.1524)
    (zone_clearance 0.3)
    (zone_45_only no)
    (trace_min 0.1524)
    (via_size 0.381)
    (via_drill 0.254)
    (via_min_size 0.381)
    (via_min_drill 0.254)
    (user_via 0.4 0.254)
    (user_via 0.6 0.4)
    (user_via 0.8 0.6)
    (user_via 1 0.8)
    (user_via 1.3 1)
    (user_via 1.5 1.2)
    (user_via 1.7 1.4)
    (user_via 1.9 1.6)
    (uvia_size 0.381)
    (uvia_drill 0.254)
    (uvias_allowed no)
    (uvia_min_size 0.381)
    (uvia_min_drill 0.254)
    (edge_width 0.15)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 0.65 1.05)
    (pad_drill 0)
    (pad_to_mask_clearance 0.1)
    (solder_mask_min_width 0.1)
    (pad_to_paste_clearance_ratio -0.15)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions true)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "OSH_Park_2_layer_plots"))
  )
  (net 0 "")
  (net 1 /VIN)
  (net 2 /VSS)
  (net 3 /VOUT)
  (net_class Default "This is the default net class."
    (clearance 0.1524)
    (trace_width 0.1524)
    (via_dia 0.381)
    (via_drill 0.254)
    (uvia_dia 0.381)
    (uvia_drill 0.254)
    (add_net /VIN)
    (add_net /VOUT)
    (add_net /VSS)
  )
  (module SquantorIC:SOT23-3-Microchip-TT (layer F.Cu) (tedit 5CCB5358)
    (at 147.3 93.6)
    (fp_text reference U1 (at 0 -2.6) (layer F.SilkS))
    (fp_text value reference3pin (at 0 2.8) (layer F.Fab))
    (pad 3 smd rect (at 0 -1.15) (size 0.65 1.05) (layers F.Cu F.Paste F.Mask)
      (net 2 /VSS) (zone_connect 2))
    (pad 2 smd rect (at 0.95 1.15) (size 0.65 1.05) (layers F.Cu F.Paste F.Mask)
      (net 3 /VOUT))
    (pad 1 smd rect (at -0.95 1.15) (size 0.65 1.05) (layers F.Cu F.Paste F.Mask)
      (net 1 /VIN))
  )
  (module SquantorConnectorsNamed:reference_input (layer B.Cu) (tedit 5CCB5024)
    (at 142.24 93.98 270)
    (descr "PIN HEADER")
    (tags "PIN HEADER")
    (attr virtual)
    (fp_text reference J2 (at 2.12 -2.26 90) (layer B.SilkS))
    (fp_text value reference_input (at 0 -2.2 90) (layer B.Fab) hide)
    (fp_text user VSS (at 3.52 -2.36 180) (layer B.SilkS))
    (fp_text user VIN (at -4.48 -2.36 180) (layer B.SilkS))
    (pad 4 thru_hole circle (at 3.81 0 90) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 2 /VSS))
    (pad 3 thru_hole circle (at 1.27 0 90) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 2 /VSS))
    (pad 2 thru_hole circle (at -1.27 0 90) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 1 /VIN))
    (pad 1 thru_hole rect (at -3.81 0 90) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 1 /VIN))
  )
  (module SquantorConnectorsNamed:reference_output (layer B.Cu) (tedit 5CCB4FA4)
    (at 152.4 93.98 90)
    (descr "PIN HEADER")
    (tags "PIN HEADER")
    (attr virtual)
    (fp_text reference J1 (at -2.12 -2.1 90) (layer B.SilkS))
    (fp_text value reference_output (at 0 -2.2 90) (layer B.Fab) hide)
    (fp_text user VOUT (at 4.48 -2.6 180) (layer B.SilkS))
    (fp_text user VSS (at -3.52 -2.4 180) (layer B.SilkS))
    (pad 4 thru_hole circle (at 3.81 0 270) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 3 /VOUT))
    (pad 3 thru_hole circle (at 1.27 0 270) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 3 /VOUT))
    (pad 2 thru_hole circle (at -1.27 0 270) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 2 /VSS))
    (pad 1 thru_hole rect (at -3.81 0 270) (size 1.3 1.3) (drill 1) (layers *.Cu *.Mask)
      (net 2 /VSS))
  )
  (module SquantorRcl:C_0805+0603 (layer F.Cu) (tedit 5CCB4DCF)
    (at 150 93.575 90)
    (descr "Capacitor SMD 0805 and 0603 pad sizes, reflow soldering, based on AVX dimensions")
    (tags "capacitor 0805 0603 mixed")
    (attr smd)
    (fp_text reference C2 (at -2.725 0 90) (layer F.SilkS))
    (fp_text value TBD (at 0 2.1 90) (layer F.Fab))
    (pad 1 smd rect (at -0.925 0 90) (size 1.15 1.25) (layers F.Cu F.Paste F.Mask)
      (net 3 /VOUT))
    (pad 2 smd rect (at 0.925 0 90) (size 1.15 1.25) (layers F.Cu F.Paste F.Mask)
      (net 2 /VSS))
    (model Capacitors_SMD.3dshapes/C_0805.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SquantorRcl:C_0805+0603 (layer F.Cu) (tedit 5CCB4DCF)
    (at 144.6 93.575 90)
    (descr "Capacitor SMD 0805 and 0603 pad sizes, reflow soldering, based on AVX dimensions")
    (tags "capacitor 0805 0603 mixed")
    (attr smd)
    (fp_text reference C1 (at -2.725 0 90) (layer F.SilkS))
    (fp_text value TBD (at 0 2.1 90) (layer F.Fab))
    (pad 1 smd rect (at -0.925 0 90) (size 1.15 1.25) (layers F.Cu F.Paste F.Mask)
      (net 1 /VIN))
    (pad 2 smd rect (at 0.925 0 90) (size 1.15 1.25) (layers F.Cu F.Paste F.Mask)
      (net 2 /VSS))
    (model Capacitors_SMD.3dshapes/C_0805.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Symbols:OSHW-Symbol_6.7x6mm_SilkScreen (layer B.Cu) (tedit 0)
    (at 147.3 92.5 180)
    (descr "Open Source Hardware Symbol")
    (tags "Logo Symbol OSHW")
    (attr virtual)
    (fp_text reference N1 (at 0 0) (layer B.SilkS) hide)
    (fp_text value OHWLOGO (at 0.75 0) (layer B.Fab) hide)
  )
  (module SquantorLabels:Label_version (layer F.Cu) (tedit 5B5A1E49)
    (at 147.15 98.7)
    (fp_text reference N2 (at 0 1.4) (layer F.Fab) hide)
    (fp_text value 20190505 (at -0.4 -0.1) (layer B.SilkS))
    (fp_text user V: (at 3.2 -0.1) (layer B.SilkS))
  )
  (gr_line (start 140.7 99.3) (end 140.7 88.7) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 153.9 99.3) (end 140.7 99.3) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 153.9 88.7) (end 153.9 99.3) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 140.7 88.7) (end 153.9 88.7) (layer Edge.Cuts) (width 0.15))
  (zone (net 2) (net_name /VSS) (layer B.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.3))
    (min_thickness 0.2)
    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 140.7 88.7) (xy 153.9 88.7) (xy 153.9 99.3) (xy 140.7 99.3)
      )
    )
  )
  (zone (net 2) (net_name /VSS) (layer F.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.3))
    (min_thickness 0.2)
    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 140.7 88.7) (xy 153.9 88.7) (xy 153.9 99.3) (xy 140.7 99.3)
      )
    )
  )
)
