Altium

Design Rule Verification Report

Date:		4/7/2017
Time:		9:58:44 AM
Elapsed Time:		00:00:01
Filename:		C:\Users\rrobles\Documents\_Reconyx\Model 9 Hardware\RCNX Exchanger Test R100\RCNX Exchanger Test R100.PcbDoc

Warnings:		0
Rule Violations:		1

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=10mil) (InNamedPolygon('Top Layer-GND')),(All)	0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Bottom Layer-GND')),(All)	0
Clearance Constraint (Gap=6mil) (All),(All)	0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Mid-Layer 1-GND')),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=3mil) (Max=50mil) (Preferred=10mil) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=12mil) (Air Gap=10mil) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=5mil) (All)	0
Hole Size Constraint (Min=6mil) (Max=125mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=2.5mil) (All),(All)	0
Silk To Solder Mask (Clearance=3mil) (IsPad),(All)	1
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1500mil) (Prefered=500mil) (All)	0
Total	1

Silk To Solder Mask (Clearance=3mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 3mil) Between Track (1641.5mil,1025mil)(1641.5mil,2350mil) on Top Overlay And Pad POWER-1(1621.331mil,1626.941mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]