(kicad_pcb (version 4) (host pcbnew 4.0.4-1.fc24-product)
  (general
    (links 13)
    (no_connects 0)
    (area 79.625 81.34 175.357143 133.39)
    (thickness 1.6)
    (drawings 6)
    (tracks 63)
    (zones 0)
    (modules 11)
    (nets 8)
  )
  (page A4)
  (title_block
    (title "CCR 24V PSU")
    (rev 2)
    (company Westnet)
  )
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.1)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 3 3)
    (pad_drill 1.6)
    (pad_to_mask_clearance 0)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 "Net-(C1-Pad1)")
  (net 2 "Net-(D1-Pad2)")
  (net 3 "Net-(D1-Pad4)")
  (net 4 "Net-(F1-Pad1)")
  (net 5 "Net-(F1-Pad2)")
  (net 6 "Net-(L1-Pad4)")
  (net 7 GND)
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
  )
  (net_class big ""
    (clearance 1)
    (trace_width 2.5)
    (via_dia 1.2)
    (via_drill 1)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net GND)
    (add_net "Net-(C1-Pad1)")
    (add_net "Net-(D1-Pad2)")
    (add_net "Net-(D1-Pad4)")
    (add_net "Net-(F1-Pad1)")
    (add_net "Net-(F1-Pad2)")
    (add_net "Net-(L1-Pad4)")
  )
  (module Mounting_Holes:MountingHole_3.2mm_M3_Pad (layer F.Cu) (tedit 581B58CB)
    (at 93.1 127.315)
    (descr "Mounting Hole 3.2mm, M3")
    (tags "mounting hole 3.2mm m3")
    (fp_text reference P3 (at 0 -4.2) (layer F.SilkS) hide)
    (fp_text value CONN_01X01 (at 0 4.2) (layer F.Fab) hide)
    (pad 1 thru_hole circle (at 0 0) (size 6.4 6.4) (drill 3.2) (layers *.Cu *.Mask F.SilkS)
      (net 7 GND))
  )
  (module Mounting_Holes:MountingHole_3.2mm_M3_Pad (layer F.Cu) (tedit 581B5902)
    (at 93.1 87.315)
    (descr "Mounting Hole 3.2mm, M3")
    (tags "mounting hole 3.2mm m3")
    (fp_text reference P4 (at 0 -4.2) (layer F.SilkS) hide)
    (fp_text value CONN_01X01 (at 0 4.2) (layer F.Fab) hide)
    (pad 1 thru_hole circle (at 0 0) (size 6.4 6.4) (drill 3.2) (layers *.Cu *.Mask F.SilkS)
      (net 7 GND))
  )
  (module Mounting_Holes:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 581B58F0)
    (at 165 87.315)
    (descr "Mounting Hole 3.2mm, no annular, M3")
    (tags "mounting hole 3.2mm no annular m3")
    (fp_text reference REF** (at 0 -4.2) (layer F.SilkS) hide)
    (fp_text value MountingHole_3.2mm_M3 (at 0 4.2) (layer F.Fab) hide)
    (pad "" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask F.SilkS))
  )
  (module Capacitors_ThroughHole:C_Radial_D10_L13_P5 (layer F.Cu) (tedit 0)
    (at 161.29 101.6 90)
    (descr "Radial Electrolytic Capacitor Diameter 10mm x Length 13mm, Pitch 5mm")
    (tags "Electrolytic Capacitor")
    (fp_text reference C1 (at 2.5 -6.3 90) (layer F.SilkS))
    (fp_text value CP (at 2.5 6.3 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
      (net 1 "Net-(C1-Pad1)"))
    (pad 2 thru_hole circle (at 5 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
      (net 7 GND))
    (model Capacitors_ThroughHole.3dshapes/C_Radial_D10_L13_P5.wrl
      (at (xyz 0.0984252 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 90))
    )
  )
  (module project:GBPC-W (layer F.Cu) (tedit 583C16C0)
    (at 137 106)
    (fp_text reference BR1 (at 0.16 -12.655) (layer F.SilkS))
    (fp_text value "Bridge Rectifier" (at -0.475 11.475) (layer F.Fab))
    (pad 1 thru_hole circle (at 9 -9) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask)
      (net 7 GND))
    (pad 2 thru_hole circle (at 9 9) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask)
      (net 2 "Net-(D1-Pad2)"))
    (pad 3 thru_hole circle (at -2.4 9) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask)
      (net 1 "Net-(C1-Pad1)"))
    (pad 4 thru_hole circle (at -9 -9) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask)
      (net 3 "Net-(D1-Pad4)"))
    (pad "" np_thru_hole circle (at 0 0) (size 5.5 5.5) (drill 5.5) (layers *.Cu *.Mask))
  )
  (module project:649-fuse (layer F.Cu) (tedit 583711D0)
    (at 105.41 96.52)
    (fp_text reference F1 (at -3.81 -2.54) (layer F.SilkS))
    (fp_text value 6.3A (at 0 -5.715) (layer F.SilkS))
    (pad 1 thru_hole circle (at -7.5 0) (size 2.5 2.5) (drill 1.3) (layers *.Cu *.Mask)
      (net 4 "Net-(F1-Pad1)"))
    (pad 2 thru_hole circle (at 7.5 0) (size 2.5 2.5) (drill 1.3) (layers *.Cu *.Mask)
      (net 5 "Net-(F1-Pad2)"))
    (pad "" np_thru_hole circle (at 0 0) (size 2.6 2.6) (drill 2.6) (layers *.Cu *.Mask))
  )
  (module project:WE-CMB (layer F.Cu) (tedit 58371190)
    (at 113.03 113.03 270)
    (fp_text reference L1 (at 0 2.54 270) (layer F.SilkS))
    (fp_text value Choke (at 0 -2.54 270) (layer F.Fab))
    (pad 1 thru_hole circle (at -5 2.25 270) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 5 "Net-(F1-Pad2)"))
    (pad 2 thru_hole circle (at -5 -2.25 270) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 3 "Net-(D1-Pad4)"))
    (pad 3 thru_hole circle (at 5 -2.25 270) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 2 "Net-(D1-Pad2)"))
    (pad 4 thru_hole circle (at 5 2.25 270) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 6 "Net-(L1-Pad4)"))
  )
  (module project:MC1,5-2-G-3,81 (layer F.Cu) (tedit 581B561F)
    (at 91 107 270)
    (fp_text reference Input (at 0 -2.6 270) (layer F.SilkS))
    (fp_text value CONN_01X02 (at 0 9.6 270) (layer F.Fab) hide)
    (pad 1 thru_hole circle (at -1.905 0 270) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask)
      (net 4 "Net-(F1-Pad1)"))
    (pad 2 thru_hole circle (at 1.905 0 270) (size 2.5 2.5) (drill 1.2) (layers *.Cu *.Mask)
      (net 6 "Net-(L1-Pad4)"))
  )
  (module Diodes_ThroughHole:Diode_DO-201AD_Horizontal_RM15 (layer F.Cu) (tedit 58371199)
    (at 100.33 106.68 270)
    (descr "Diode DO-201AD Horizontal")
    (tags "Diode DO-201AD Horizontal SB320 SB340 SB360")
    (fp_text reference D1 (at 7.62 0 270) (layer F.SilkS))
    (fp_text value VR (at 7.82922 -4.82896 270) (layer F.Fab) hide)
    (pad 2 thru_hole circle (at 15.24122 -0.00296 90) (size 2.54 2.54) (drill 1.50114) (layers *.Cu *.Mask F.SilkS)
      (net 6 "Net-(L1-Pad4)"))
    (pad 1 thru_hole rect (at 0.00122 -0.00296 90) (size 2.54 2.54) (drill 1.50114) (layers *.Cu *.Mask F.SilkS)
      (net 5 "Net-(F1-Pad2)"))
  )
  (module project:V-OUT (layer F.Cu) (tedit 5837114A)
    (at 162.56 115.57 90)
    (fp_text reference Output (at 0 -5.08 90) (layer F.SilkS))
    (fp_text value CONN_01X02 (at 0 -2.286 90) (layer F.Fab) hide)
    (fp_text user - (at 4.445 3.81 90) (layer F.SilkS))
    (fp_text user + (at -5.08 3.81 90) (layer F.SilkS))
    (pad 1 thru_hole circle (at -3 0 90) (size 3 3) (drill 1.6) (layers *.Cu *.Mask)
      (net 1 "Net-(C1-Pad1)"))
    (pad 2 thru_hole circle (at 3 0 90) (size 3 3) (drill 1.6) (layers *.Cu *.Mask)
      (net 7 GND))
  )
  (module Mounting_Holes:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 581B58DE)
    (at 165 127.315)
    (descr "Mounting Hole 3.2mm, no annular, M3")
    (tags "mounting hole 3.2mm no annular m3")
    (fp_text reference REF** (at 0 -4.2) (layer F.SilkS) hide)
    (fp_text value MountingHole_3.2mm_M3 (at 0 4.2) (layer F.Fab) hide)
    (pad "" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask F.SilkS))
  )
  (gr_text "© 2016 Westnet" (at 158.75 127.635) (layer F.SilkS))
  (gr_text "CCR 24V PSU rev2" (at 138.43 86.995) (layer F.SilkS))
  (gr_line (start 85.09 132.08) (end 85.09 82.55) (angle 90) (layer Edge.Cuts) (width 0.1))
  (gr_line (start 171.45 132.08) (end 85.09 132.08) (angle 90) (layer Edge.Cuts) (width 0.1))
  (gr_line (start 171.45 82.55) (end 171.45 132.08) (angle 90) (layer Edge.Cuts) (width 0.1))
  (gr_line (start 85.09 82.55) (end 171.45 82.55) (angle 90) (layer Edge.Cuts) (width 0.1))
  (zone (net 7) (net_name GND) (layer B.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 171.45 132.08) (xy 85.09 132.08) (xy 85.09 82.55) (xy 171.45 82.55)
      )
    )
  )
)
