(kicad_pcb (version 4) (host pcbnew 4.0.6)
  (general
    (links 34)
    (no_connects 0)
    (area 134.412667 93.723 162.259334 120.753)
    (thickness 1.6)
    (drawings 9)
    (tracks 112)
    (zones 0)
    (modules 4)
    (nets 19)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (44 Edge.Cuts user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFEFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 "Net-(J1-Pad1)")
  (net 2 "Net-(J1-Pad2)")
  (net 3 "Net-(J1-Pad3)")
  (net 4 "Net-(J1-Pad4)")
  (net 5 "Net-(J1-Pad5)")
  (net 6 "Net-(J1-Pad6)")
  (net 7 "Net-(J1-Pad7)")
  (net 8 GND)
  (net 9 "Net-(J1-Pad9)")
  (net 10 "Net-(J2-Pad1)")
  (net 11 "Net-(J2-Pad2)")
  (net 12 "Net-(J2-Pad3)")
  (net 13 "Net-(J2-Pad4)")
  (net 14 "Net-(J2-Pad5)")
  (net 15 "Net-(J2-Pad6)")
  (net 16 "Net-(J2-Pad7)")
  (net 17 "Net-(J2-Pad8)")
  (net 18 "Net-(J2-Pad9)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net GND)
    (add_net "Net-(J1-Pad1)")
    (add_net "Net-(J1-Pad2)")
    (add_net "Net-(J1-Pad3)")
    (add_net "Net-(J1-Pad4)")
    (add_net "Net-(J1-Pad5)")
    (add_net "Net-(J1-Pad6)")
    (add_net "Net-(J1-Pad7)")
    (add_net "Net-(J1-Pad9)")
    (add_net "Net-(J2-Pad1)")
    (add_net "Net-(J2-Pad2)")
    (add_net "Net-(J2-Pad3)")
    (add_net "Net-(J2-Pad4)")
    (add_net "Net-(J2-Pad5)")
    (add_net "Net-(J2-Pad6)")
    (add_net "Net-(J2-Pad7)")
    (add_net "Net-(J2-Pad8)")
    (add_net "Net-(J2-Pad9)")
  )
  (module Pin_Headers:Pin_Header_Straight_1x09_Pitch2.54mm (layer F.Cu) (tedit 5AD20717)
    (at 139.446 97.028)
    (descr "Through hole straight pin header, 1x09, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x09 2.54mm single row")
    (fp_text reference J1 (at 3.048 0) (layer F.SilkS) hide)
    (fp_text value CONN_01X09 (at 0 22.65) (layer F.Fab))
    (fp_text user %R (at 0 10.16 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 "Net-(J1-Pad1)"))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 "Net-(J1-Pad2)"))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 "Net-(J1-Pad3)"))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 "Net-(J1-Pad4)"))
    (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 "Net-(J1-Pad5)"))
    (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 "Net-(J1-Pad6)"))
    (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 7 "Net-(J1-Pad7)"))
    (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 8 GND))
    (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 9 "Net-(J1-Pad9)"))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x09_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Pin_Headers:Pin_Header_Straight_1x09_Pitch2.54mm (layer F.Cu) (tedit 5AD20722)
    (at 157.226 97.028)
    (descr "Through hole straight pin header, 1x09, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x09 2.54mm single row")
    (fp_text reference J2 (at 0 -2.33) (layer F.SilkS) hide)
    (fp_text value CONN_01X09 (at 0 22.65) (layer F.Fab))
    (fp_text user %R (at 0 10.16 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 10 "Net-(J2-Pad1)"))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 11 "Net-(J2-Pad2)"))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 12 "Net-(J2-Pad3)"))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 13 "Net-(J2-Pad4)"))
    (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 14 "Net-(J2-Pad5)"))
    (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 15 "Net-(J2-Pad6)"))
    (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 16 "Net-(J2-Pad7)"))
    (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 17 "Net-(J2-Pad8)"))
    (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 18 "Net-(J2-Pad9)"))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x09_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Housings_SOIC:SOIC-18W_7.5x11.6mm_Pitch1.27mm (layer F.Cu) (tedit 5ABE78C5)
    (at 148.336 107.95)
    (descr "18-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
    (tags "SOIC 1.27")
    (attr smd)
    (fp_text reference U1 (at 0 -6.875) (layer F.SilkS))
    (fp_text value MIC2981 (at 0.0689 8.4264) (layer F.Fab))
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 1 smd rect (at -4.7 -5.08) (size 2 0.6) (layers F.Cu F.Mask)
      (net 1 "Net-(J1-Pad1)"))
    (pad 2 smd rect (at -4.7 -3.81) (size 2 0.6) (layers F.Cu F.Mask)
      (net 2 "Net-(J1-Pad2)"))
    (pad 3 smd rect (at -4.7 -2.54) (size 2 0.6) (layers F.Cu F.Mask)
      (net 3 "Net-(J1-Pad3)"))
    (pad 4 smd rect (at -4.7 -1.27) (size 2 0.6) (layers F.Cu F.Mask)
      (net 4 "Net-(J1-Pad4)"))
    (pad 5 smd rect (at -4.7 0) (size 2 0.6) (layers F.Cu F.Mask)
      (net 5 "Net-(J1-Pad5)"))
    (pad 6 smd rect (at -4.7 1.27) (size 2 0.6) (layers F.Cu F.Mask)
      (net 6 "Net-(J1-Pad6)"))
    (pad 7 smd rect (at -4.7 2.54) (size 2 0.6) (layers F.Cu F.Mask)
      (net 7 "Net-(J1-Pad7)"))
    (pad 8 smd rect (at -4.7 3.81) (size 2 0.6) (layers F.Cu F.Mask)
      (net 8 GND))
    (pad 9 smd rect (at -4.7 5.08) (size 2 0.6) (layers F.Cu F.Mask)
      (net 9 "Net-(J1-Pad9)"))
    (pad 10 smd rect (at 4.7 5.08) (size 2 0.6) (layers F.Cu F.Mask)
      (net 18 "Net-(J2-Pad9)"))
    (pad 11 smd rect (at 4.7 3.81) (size 2 0.6) (layers F.Cu F.Mask)
      (net 17 "Net-(J2-Pad8)"))
    (pad 12 smd rect (at 4.7 2.54) (size 2 0.6) (layers F.Cu F.Mask)
      (net 16 "Net-(J2-Pad7)"))
    (pad 13 smd rect (at 4.7 1.27) (size 2 0.6) (layers F.Cu F.Mask)
      (net 15 "Net-(J2-Pad6)"))
    (pad 14 smd rect (at 4.7 0) (size 2 0.6) (layers F.Cu F.Mask)
      (net 14 "Net-(J2-Pad5)"))
    (pad 15 smd rect (at 4.7 -1.27) (size 2 0.6) (layers F.Cu F.Mask)
      (net 13 "Net-(J2-Pad4)"))
    (pad 16 smd rect (at 4.7 -2.54) (size 2 0.6) (layers F.Cu F.Mask)
      (net 12 "Net-(J2-Pad3)"))
    (pad 17 smd rect (at 4.7 -3.81) (size 2 0.6) (layers F.Cu F.Mask)
      (net 11 "Net-(J2-Pad2)"))
    (pad 18 smd rect (at 4.7 -5.08) (size 2 0.6) (layers F.Cu F.Mask)
      (net 10 "Net-(J2-Pad1)"))
    (model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-18W_7.5x11.6mm_Pitch1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer B.Cu) (tedit 5ABE78CD)
    (at 148.336 107.442 180)
    (descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
    (tags "SOIC 1.27")
    (attr smd)
    (fp_text reference U2 (at 0 6 180) (layer B.SilkS))
    (fp_text value HEF4794B (at -0.0811 -7.0364 180) (layer B.Fab))
    (fp_text user %R (at 0 0 180) (layer B.Fab))
    (pad 1 smd rect (at -2.7 4.445 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 10 "Net-(J2-Pad1)"))
    (pad 2 smd rect (at -2.7 3.175 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 11 "Net-(J2-Pad2)"))
    (pad 3 smd rect (at -2.7 1.905 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 12 "Net-(J2-Pad3)"))
    (pad 4 smd rect (at -2.7 0.635 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 13 "Net-(J2-Pad4)"))
    (pad 5 smd rect (at -2.7 -0.635 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 14 "Net-(J2-Pad5)"))
    (pad 6 smd rect (at -2.7 -1.905 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 15 "Net-(J2-Pad6)"))
    (pad 7 smd rect (at -2.7 -3.175 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 16 "Net-(J2-Pad7)"))
    (pad 8 smd rect (at -2.7 -4.445 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 17 "Net-(J2-Pad8)"))
    (pad 9 smd rect (at 2.7 -4.445 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 8 GND))
    (pad 10 smd rect (at 2.7 -3.175 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 7 "Net-(J1-Pad7)"))
    (pad 11 smd rect (at 2.7 -1.905 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 6 "Net-(J1-Pad6)"))
    (pad 12 smd rect (at 2.7 -0.635 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 5 "Net-(J1-Pad5)"))
    (pad 13 smd rect (at 2.7 0.635 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 4 "Net-(J1-Pad4)"))
    (pad 14 smd rect (at 2.7 1.905 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 3 "Net-(J1-Pad3)"))
    (pad 15 smd rect (at 2.7 3.175 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 2 "Net-(J1-Pad2)"))
    (pad 16 smd rect (at 2.7 4.445 180) (size 1.5 0.6) (layers B.Cu B.Mask)
      (net 1 "Net-(J1-Pad1)"))
    (model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_text "v1.1 2018-04" (at 148.336 106.934 90) (layer F.SilkS))
  (gr_text 1 (at 153.67 97.028) (layer B.SilkS))
  (gr_text SOIC-16 (at 148.844 113.792) (layer B.SilkS))
  (gr_text SOIC-18W (at 148.844 114.808) (layer F.SilkS))
  (gr_text 1 (at 142.494 97.028) (layer F.SilkS))
  (gr_line (start 137.942 118.75) (end 137.942 95.4) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 158.75 118.75) (end 137.942 118.75) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 158.704 95.25) (end 158.704 118.75) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 137.92 95.358) (end 158.7 95.358) (angle 90) (layer Edge.Cuts) (width 0.15))
)
