(kicad_pcb (version 20171130) (host pcbnew "(5.1.6-0-10_14)")
  (general
    (thickness 1.6)
    (drawings 6)
    (tracks 10)
    (zones 0)
    (modules 5)
    (nets 5)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (via_size 0.8)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.05)
    (segment_width 0.2)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.12)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.05)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes true)
      (usegerberadvancedattributes true)
      (creategerberjobfile true)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 "Net-(C1-Pad2)")
  (net 2 "Net-(C1-Pad1)")
  (net 3 "Net-(C2-Pad2)")
  (net 4 "Net-(C2-Pad1)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.8)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(C1-Pad1)")
    (add_net "Net-(C1-Pad2)")
    (add_net "Net-(C2-Pad1)")
    (add_net "Net-(C2-Pad2)")
  )
  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 5EC1EA8B)
    (at 109.22 71.12)
    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x02 2.54mm single row")
    (fp_text reference J1 (at 0 -2.33) (layer F.SilkS) hide)
    (fp_text value Conn_01x02_Female (at 0 4.87) (layer F.Fab) hide)
    (fp_text user %R (at 0 1.27 90) (layer F.Fab))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 "Net-(C2-Pad1)"))
    (pad 1 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 "Net-(C1-Pad1)"))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 5EC1EA73)
    (at 121.285 73.66 180)
    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x02 2.54mm single row")
    (fp_text reference J2 (at 0 -2.33 180) (layer F.SilkS) hide)
    (fp_text value Conn_01x02_Female (at 0 4.87 180) (layer F.Fab) hide)
    (fp_text user %R (at 0 1.27 270) (layer F.Fab))
    (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 "Net-(C1-Pad2)"))
    (pad 1 thru_hole circle (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 "Net-(C2-Pad2)"))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Crystal:Crystal_SMD_G8-2Pin_3.2x1.5mm (layer F.Cu) (tedit 5A0FD1B2)
    (at 117.475 72.39 270)
    (descr "SMD Crystal G8, 3.2x1.5mm^2 package")
    (tags "SMD SMT crystal")
    (attr smd)
    (fp_text reference Y1 (at 0 -1.95 90) (layer F.SilkS) hide)
    (fp_text value Crystal (at 0 1.95 90) (layer F.Fab) hide)
    (fp_text user %R (at 0 0 90) (layer F.Fab) hide)
    (pad 2 smd rect (at 1.25 0 270) (size 1 1.8) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(C2-Pad2)"))
    (pad 1 smd rect (at -1.25 0 270) (size 1 1.8) (layers F.Cu F.Paste F.Mask)
      (net 1 "Net-(C1-Pad2)"))
    (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_G8-2Pin_3.2x1.5mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitor_SMD:C_0805_2012Metric (layer F.Cu) (tedit 5B36C52B)
    (at 113.665 73.66)
    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
    (tags capacitor)
    (attr smd)
    (fp_text reference C2 (at 0 -1.65) (layer F.SilkS) hide)
    (fp_text value C_Small (at 0 1.65) (layer F.Fab) hide)
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 2 smd roundrect (at 0.9375 0) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 3 "Net-(C2-Pad2)"))
    (pad 1 smd roundrect (at -0.9375 0) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 4 "Net-(C2-Pad1)"))
    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitor_SMD:C_0805_2012Metric (layer F.Cu) (tedit 5B36C52B)
    (at 113.665 71.12)
    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
    (tags capacitor)
    (attr smd)
    (fp_text reference C1 (at 0 -1.65) (layer F.SilkS) hide)
    (fp_text value C_Small (at 0 1.65) (layer F.Fab) hide)
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 2 smd roundrect (at 0.9375 0) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 "Net-(C1-Pad2)"))
    (pad 1 smd roundrect (at -0.9375 0) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 2 "Net-(C1-Pad1)"))
    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_text "G8 Crystal\nDirect To\nPower Rails" (at 115.316 72.39) (layer B.SilkS))
  (gr_line (start 107.315 75.565) (end 107.315 69.215) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 123.19 75.565) (end 107.315 75.565) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 123.19 69.215) (end 123.19 75.565) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 107.315 69.215) (end 123.19 69.215) (layer Edge.Cuts) (width 0.05))
  (dimension 12.065 (width 0.15) (layer Dwgs.User)
    (gr_text "12.065 mm" (at 115.2525 79.405) (layer Dwgs.User))
    (feature1 (pts (xy 121.285 73.66) (xy 121.285 78.691421)))
    (feature2 (pts (xy 109.22 73.66) (xy 109.22 78.691421)))
    (crossbar (pts (xy 109.22 78.105) (xy 121.285 78.105)))
    (arrow1a (pts (xy 121.285 78.105) (xy 120.158496 78.691421)))
    (arrow1b (pts (xy 121.285 78.105) (xy 120.158496 77.518579)))
    (arrow2a (pts (xy 109.22 78.105) (xy 110.346504 78.691421)))
    (arrow2b (pts (xy 109.22 78.105) (xy 110.346504 77.518579)))
  )
)
