(kicad_pcb (version 20171130) (host pcbnew "(5.1.2-1)-1")
  (general
    (thickness 1.6)
    (drawings 4)
    (tracks 40)
    (zones 0)
    (modules 2)
    (nets 9)
  )
  (page A4)
  (title_block
    (date 2020-10-14)
  )
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user hide)
    (33 F.Adhes user hide)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user hide)
    (39 F.Mask user)
    (40 Dwgs.User user hide)
    (41 Cmts.User user hide)
    (44 Edge.Cuts user)
    (45 Margin user hide)
    (46 B.CrtYd user hide)
    (47 F.CrtYd user hide)
    (48 B.Fab user hide)
    (49 F.Fab user hide)
  )
  (setup
    (last_trace_width 0.1524)
    (user_trace_width 0.25)
    (user_trace_width 0.28)
    (user_trace_width 0.3)
    (user_trace_width 0.35)
    (user_trace_width 0.4)
    (trace_clearance 0.1524)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.1524)
    (via_size 0.508)
    (via_drill 0.254)
    (via_min_size 0.508)
    (via_min_drill 0.254)
    (uvia_size 0.508)
    (uvia_drill 0.254)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (edge_width 0.15)
    (segment_width 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.75 0.6)
    (pad_drill 0)
    (pad_to_mask_clearance 0.051)
    (solder_mask_min_width 0.25)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x010f0_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer false)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "gerbers/"))
  )
  (net 0 "")
  (net 1 "Net-(J44-Pad1)")
  (net 2 "Net-(J44-Pad5)")
  (net 3 "Net-(J44-Pad2)")
  (net 4 "Net-(J44-Pad6)")
  (net 5 "Net-(J44-Pad3)")
  (net 6 "Net-(J44-Pad7)")
  (net 7 "Net-(J44-Pad4)")
  (net 8 "Net-(J44-Pad8)")
  (net_class Default "This is the default net class."
    (clearance 0.1524)
    (trace_width 0.1524)
    (via_dia 0.508)
    (via_drill 0.254)
    (uvia_dia 0.508)
    (uvia_drill 0.254)
  )
  (net_class SMD ""
    (clearance 0.1524)
    (trace_width 0.254)
    (via_dia 0.508)
    (via_drill 0.254)
    (uvia_dia 0.508)
    (uvia_drill 0.254)
  )
  (net_class grounds ""
    (clearance 0.254)
    (trace_width 1)
    (via_dia 0.762)
    (via_drill 0.381)
    (uvia_dia 0.762)
    (uvia_drill 0.381)
  )
  (net_class power ""
    (clearance 0.254)
    (trace_width 1)
    (via_dia 0.762)
    (via_drill 0.254)
    (uvia_dia 0.508)
    (uvia_drill 0.254)
  )
  (net_class signal ""
    (clearance 0.2)
    (trace_width 0.6096)
    (via_dia 0.762)
    (via_drill 0.381)
    (uvia_dia 0.762)
    (uvia_drill 0.381)
  )
  (net_class soic ""
    (clearance 0.1524)
    (trace_width 0.4)
    (via_dia 0.508)
    (via_drill 0.254)
    (uvia_dia 0.508)
    (uvia_drill 0.254)
    (add_net "Net-(J44-Pad1)")
    (add_net "Net-(J44-Pad2)")
    (add_net "Net-(J44-Pad3)")
    (add_net "Net-(J44-Pad4)")
    (add_net "Net-(J44-Pad5)")
    (add_net "Net-(J44-Pad6)")
    (add_net "Net-(J44-Pad7)")
    (add_net "Net-(J44-Pad8)")
  )
  (module SMC_generic:DIP-8adapt (layer F.Cu) (tedit 5D855640)
    (at 256.5 85.06 270)
    (descr "8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket")
    (tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket")
    (fp_text reference J44 (at 3.81 -2.33 90) (layer F.SilkS) hide)
    (fp_text value DIP-8 (at 3.81 9.95 90) (layer F.Fab))
    (fp_text user %R (at 3.81 3.81 90) (layer F.Fab))
    (pad 8 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 8 "Net-(J44-Pad8)"))
    (pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 7 "Net-(J44-Pad4)"))
    (pad 7 thru_hole oval (at 7.62 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 6 "Net-(J44-Pad7)"))
    (pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 5 "Net-(J44-Pad3)"))
    (pad 6 thru_hole oval (at 7.62 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 4 "Net-(J44-Pad6)"))
    (pad 2 thru_hole oval (at 0 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 3 "Net-(J44-Pad2)"))
    (pad 5 thru_hole oval (at 7.62 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 2 "Net-(J44-Pad5)"))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 1 "Net-(J44-Pad1)"))
    (model ${KIPRJMOD}/Package_DIP.3dshapes/DIP-8_W7.62mm_Socket.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module SMC_generic:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5E18F218)
    (at 252.69 88.87 180)
    (descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
    (tags "SOIC SO")
    (attr smd)
    (fp_text reference U10 (at 0 -3.4) (layer F.SilkS) hide)
    (fp_text value OPA1611 (at 0 3.4) (layer F.Fab))
    (fp_text user 1 (at -4.3 -1.9 90 unlocked) (layer F.SilkS))
    (fp_text user %R (at 0 0) (layer F.Fab))
    (pad 8 smd roundrect (at 2.725 -1.905 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 8 "Net-(J44-Pad8)"))
    (pad 7 smd roundrect (at 2.725 -0.635 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 6 "Net-(J44-Pad7)"))
    (pad 6 smd roundrect (at 2.725 0.635 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 4 "Net-(J44-Pad6)"))
    (pad 5 smd roundrect (at 2.725 1.905 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 2 "Net-(J44-Pad5)"))
    (pad 4 smd roundrect (at -2.725 1.905 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 7 "Net-(J44-Pad4)"))
    (pad 3 smd roundrect (at -2.725 0.635 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 5 "Net-(J44-Pad3)"))
    (pad 2 smd roundrect (at -2.725 -0.635 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 3 "Net-(J44-Pad2)"))
    (pad 1 smd roundrect (at -2.725 -1.905 180) (size 2 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 "Net-(J44-Pad1)"))
    (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_line (start 247.59 83.77) (end 247.59 93.97) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 257.79 93.97) (end 247.59 93.97) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 257.79 83.77) (end 247.59 83.77) (layer Edge.Cuts) (width 0.05))
  (gr_line (start 257.79 93.97) (end 257.79 83.77) (layer Edge.Cuts) (width 0.05))
)
