Altium

Design Rule Verification Report

Date: 2/28/2020
Time: 8:10:16 PM
Elapsed Time: 00:00:00
Filename: C:\Users\grrtt\Desktop\Schoolwork fall 2019 surface\msd\MSD PCB files\MSD project\PCB1.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=10mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All) 0
SMD Neck-Down Constraint (Percent=50%) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Hole Size Constraint (Min=1mil) (Max=300mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=4.5mil) (All),(All) 0
Silk To Solder Mask (Clearance=5mil) (IsPad),(All) 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Room Sheet1 (Bounding Region = (130mil, 240mil, 6830mil, 5585mil) (InComponentClass('Sheet1')) 0
Room Sheet2 (Bounding Region = (495mil, 550mil, 6545mil, 5375mil) (InComponentClass('Sheet2')) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 0