(kicad_pcb (version 20171130) (host pcbnew "(5.0.2)-1")
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    (thickness 1.6)
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    (tracks 122)
    (zones 0)
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    (32 B.Adhes user)
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    (45 Margin user)
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    (48 B.Fab user)
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    (uvias_allowed no)
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  (net 25 /A13)
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  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.8)
    (via_drill 0.4)
    (uvia_dia 0.3)
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    (add_net /A0)
    (add_net /A1)
    (add_net /A10)
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    (add_net /A13)
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    (add_net /A6)
    (add_net /A7)
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    (add_net /D1)
    (add_net /D2)
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    (add_net /D4)
    (add_net /D5)
    (add_net /D6)
    (add_net /D7)
    (add_net /GND)
    (add_net /VCC)
    (add_net /~CE)
  )
  (module 27C512E-TO-2532S:DIL24-6-NO-OUTLINE (layer Top) (tedit 0)
    (at 156.1211 79.6036 270)
    (descr "<center><b>Dual In Line Package (DIP) Socket</b><br>Row Spacing: 0.6 inch (15.24 mm/600 mil)<br>Number of Pins: (Grid): 24 (2 x 12)<br>Pitch: 0.100 inch (2.54mm)<br>Mounting Type: Through Hole<br>Copyright ©07 Jan 2013, by:<br>\nRobert \"The R.A.T.\" Allen Turner<br>\n<a href=\"http://www.TheLittleEngineers.org/\">http://www.TheLittleEngineers.org/</a><br><a href=\"mailto:TheLittleEngineers@outlook.com\">TheLittleEngineers@outlook.com</a><br><a href=\"mailto:OurLittleEngineers@gMail.com\">OurLittleEngineers@gMail.com</a><br></center>\n<p align=\"justify\">You may use these footprints in your own projects, however, please take note that we CANNOT guarantee the accuracy of these components (nor any part of this library). We make NO guarantees that the components, footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for informational purposes only, and are used at your own discretion. By downloading these libraries, you agree that we cannot be held responsible for faulty PCBs. You should always check the footprints with a 1:1 printout. Neither Robert Allen Turner, <a href=\"http://www.TheLittleEngineers.org/\">The Little Engineers</a>, <a href=\"http://www.TheLittleEngineers.org/\">TheLittleEngineers.org,</a> <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a>, nor anyone affiliated with same shall be held responsible for any outcome resulting from the usage of these files. Should any errors be found, please contact us at one of the above email addresses and we will attempt to repair them. Unless otherwise noted, content of this library is licensed under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a> on 20 April 2019 in memory of my Father, Robert Embry Turner - I LOVE YOU DAD! Rest In Peace. Please note that the <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> domain was acquired by Robert \"The R.A.T.\" Allen Turner on December 24, 2018 from the prior owners, which happen to be his brother and nephew. As such, \"The R.A.T.\" is unable to answer any inquiries regarding any products or services of <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> prior to that date. \"The R.A.T.\" also acquired the rights to all products previously produced by <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> and its previous owners. Those products will all be released as open source, under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a>, as time and resources permit.</p>")
    (fp_text reference IC1 (at 0 0 270) (layer F.SilkS) hide)
    (fp_text value TMS2532-NO (at 0 0 270) (layer F.SilkS) hide)
    (pad 24 thru_hole rect (at -13.97 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 1 /VCC) (solder_mask_margin 0.1016))
    (pad 23 thru_hole rect (at -11.43 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 2 /A8) (solder_mask_margin 0.1016))
    (pad 22 thru_hole rect (at -8.89 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 3 /A9) (solder_mask_margin 0.1016))
    (pad 21 thru_hole rect (at -6.35 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 1 /VCC) (solder_mask_margin 0.1016))
    (pad 20 thru_hole rect (at -3.81 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 4 /~CE) (solder_mask_margin 0.1016))
    (pad 19 thru_hole rect (at -1.27 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 5 /A10) (solder_mask_margin 0.1016))
    (pad 18 thru_hole rect (at 1.27 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 6 /A11) (solder_mask_margin 0.1016))
    (pad 17 thru_hole rect (at 3.81 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 7 /D7) (solder_mask_margin 0.1016))
    (pad 16 thru_hole rect (at 6.35 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 8 /D6) (solder_mask_margin 0.1016))
    (pad 15 thru_hole rect (at 8.89 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 9 /D5) (solder_mask_margin 0.1016))
    (pad 14 thru_hole rect (at 11.43 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 10 /D4) (solder_mask_margin 0.1016))
    (pad 13 thru_hole rect (at 13.97 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 11 /D3) (solder_mask_margin 0.1016))
    (pad 12 thru_hole rect (at 13.97 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 12 /GND) (solder_mask_margin 0.1016))
    (pad 11 thru_hole rect (at 11.43 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 13 /D2) (solder_mask_margin 0.1016))
    (pad 10 thru_hole rect (at 8.89 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 14 /D1) (solder_mask_margin 0.1016))
    (pad 9 thru_hole rect (at 6.35 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 15 /D0) (solder_mask_margin 0.1016))
    (pad 8 thru_hole rect (at 3.81 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 16 /A0) (solder_mask_margin 0.1016))
    (pad 7 thru_hole rect (at 1.27 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 17 /A1) (solder_mask_margin 0.1016))
    (pad 6 thru_hole rect (at -1.27 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 18 /A2) (solder_mask_margin 0.1016))
    (pad 5 thru_hole rect (at -3.81 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 19 /A3) (solder_mask_margin 0.1016))
    (pad 4 thru_hole rect (at -6.35 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 20 /A4) (solder_mask_margin 0.1016))
    (pad 3 thru_hole rect (at -8.89 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 21 /A5) (solder_mask_margin 0.1016))
    (pad 2 thru_hole rect (at -11.43 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 22 /A6) (solder_mask_margin 0.1016))
    (pad 1 thru_hole circle (at -13.97 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 23 /A7) (solder_mask_margin 0.1016))
  )
  (module 27C512E-TO-2532S:DIL28-6-NO-OUTLINE (layer Top) (tedit 0)
    (at 158.6611 79.6036 270)
    (descr "<center><b>Dual In Line Package (DIP) Socket</b><br>Row Spacing: 0.6 inch (15.24 mm/600 mil)<br>Number of Pins: (Grid): 28 (2 x 14)<br>Pitch: 0.100 inch (2.54mm)<br>Mounting Type: Through Hole<br>Copyright ©07 Jan 2013, by:<br>\nRobert \"The R.A.T.\" Allen Turner<br>\n<a href=\"http://www.TheLittleEngineers.org/\">http://www.TheLittleEngineers.org/</a><br><a href=\"mailto:TheLittleEngineers@outlook.com\">TheLittleEngineers@outlook.com</a><br><a href=\"mailto:OurLittleEngineers@gMail.com\">OurLittleEngineers@gMail.com</a><br></center>\n<p align=\"justify\">You may use these footprints in your own projects, however, please take note that we CANNOT guarantee the accuracy of these components (nor any part of this library). We make NO guarantees that the components, footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for informational purposes only, and are used at your own discretion. By downloading these libraries, you agree that we cannot be held responsible for faulty PCBs. You should always check the footprints with a 1:1 printout. Neither Robert Allen Turner, <a href=\"http://www.TheLittleEngineers.org/\">The Little Engineers</a>, <a href=\"http://www.TheLittleEngineers.org/\">TheLittleEngineers.org,</a> <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a>, nor anyone affiliated with same shall be held responsible for any outcome resulting from the usage of these files. Should any errors be found, please contact us at one of the above email addresses and we will attempt to repair them. Unless otherwise noted, content of this library is licensed under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a> on 20 April 2019 in memory of my Father, Robert Embry Turner - I LOVE YOU DAD! Rest In Peace. Please note that the <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> domain was acquired by Robert \"The R.A.T.\" Allen Turner on December 24, 2018 from the prior owners, which happen to be his brother and nephew. As such, \"The R.A.T.\" is unable to answer any inquiries regarding any products or services of <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> prior to that date. \"The R.A.T.\" also acquired the rights to all products previously produced by <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> and its previous owners. Those products will all be released as open source, under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a>, as time and resources permit.</p>")
    (fp_text reference IC2 (at 0 0 270) (layer F.SilkS) hide)
    (fp_text value 27C512D-NO (at 0 0 270) (layer F.SilkS) hide)
    (pad 28 thru_hole circle (at -16.51 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 1 /VCC) (solder_mask_margin 0.1016))
    (pad 27 thru_hole circle (at -13.97 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 24 /A14) (solder_mask_margin 0.1016))
    (pad 26 thru_hole circle (at -11.43 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 25 /A13) (solder_mask_margin 0.1016))
    (pad 25 thru_hole circle (at -8.89 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 2 /A8) (solder_mask_margin 0.1016))
    (pad 24 thru_hole circle (at -6.35 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 3 /A9) (solder_mask_margin 0.1016))
    (pad 23 thru_hole circle (at -3.81 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 6 /A11) (solder_mask_margin 0.1016))
    (pad 22 thru_hole circle (at -1.27 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 4 /~CE) (solder_mask_margin 0.1016))
    (pad 21 thru_hole circle (at 1.27 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 5 /A10) (solder_mask_margin 0.1016))
    (pad 20 thru_hole circle (at 3.81 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 4 /~CE) (solder_mask_margin 0.1016))
    (pad 19 thru_hole circle (at 6.35 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 7 /D7) (solder_mask_margin 0.1016))
    (pad 18 thru_hole circle (at 8.89 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 8 /D6) (solder_mask_margin 0.1016))
    (pad 17 thru_hole circle (at 11.43 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 9 /D5) (solder_mask_margin 0.1016))
    (pad 16 thru_hole circle (at 13.97 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 10 /D4) (solder_mask_margin 0.1016))
    (pad 15 thru_hole circle (at 16.51 -7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 11 /D3) (solder_mask_margin 0.1016))
    (pad 14 thru_hole circle (at 16.51 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 12 /GND) (solder_mask_margin 0.1016))
    (pad 13 thru_hole circle (at 13.97 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 13 /D2) (solder_mask_margin 0.1016))
    (pad 12 thru_hole circle (at 11.43 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 14 /D1) (solder_mask_margin 0.1016))
    (pad 11 thru_hole circle (at 8.89 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 15 /D0) (solder_mask_margin 0.1016))
    (pad 10 thru_hole circle (at 6.35 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 16 /A0) (solder_mask_margin 0.1016))
    (pad 9 thru_hole circle (at 3.81 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 17 /A1) (solder_mask_margin 0.1016))
    (pad 8 thru_hole circle (at 1.27 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 18 /A2) (solder_mask_margin 0.1016))
    (pad 7 thru_hole circle (at -1.27 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 19 /A3) (solder_mask_margin 0.1016))
    (pad 6 thru_hole circle (at -3.81 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 20 /A4) (solder_mask_margin 0.1016))
    (pad 5 thru_hole circle (at -6.35 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 21 /A5) (solder_mask_margin 0.1016))
    (pad 4 thru_hole circle (at -8.89 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 22 /A6) (solder_mask_margin 0.1016))
    (pad 3 thru_hole circle (at -11.43 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 23 /A7) (solder_mask_margin 0.1016))
    (pad 2 thru_hole circle (at -13.97 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 26 /A12) (solder_mask_margin 0.1016))
    (pad 1 thru_hole rect (at -16.51 7.62) (size 1.3208 1.3208) (drill 0.8128) (layers *.Cu *.Mask)
      (net 27 /A15) (solder_mask_margin 0.1016))
  )
  (module 27C512E-TO-2532S:1X03-STAGGERED (layer Top) (tedit 0)
    (at 162.2171 101.1936 270)
    (descr "<center><b>Single In Line Package (SIP) Header</b><br>Row Spacing: 0.6 inch (15.24 mm/600 mil)<br>Number of Pins: (Grid): 3 (1 x 3)<br>Pitch: 0.100 inch (2.54mm)<br>Mounting Type: Through Hole<br>Copyright ©07 Jan 2013, by:<br>\nRobert \"The R.A.T.\" Allen Turner<br>\n<a href=\"http://www.TheLittleEngineers.org/\">http://www.TheLittleEngineers.org/</a><br><a href=\"mailto:TheLittleEngineers@outlook.com\">TheLittleEngineers@outlook.com</a><br><a href=\"mailto:OurLittleEngineers@gMail.com\">OurLittleEngineers@gMail.com</a><br></center>\n<p align=\"justify\">You may use these footprints in your own projects, however, please take note that we CANNOT guarantee the accuracy of these components (nor any part of this library). We make NO guarantees that the components, footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for informational purposes only, and are used at your own discretion. By downloading these libraries, you agree that we cannot be held responsible for faulty PCBs. You should always check the footprints with a 1:1 printout. Neither Robert Allen Turner, <a href=\"http://www.TheLittleEngineers.org/\">The Little Engineers</a>, <a href=\"http://www.TheLittleEngineers.org/\">TheLittleEngineers.org,</a> <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a>, nor anyone affiliated with same shall be held responsible for any outcome resulting from the usage of these files. Should any errors be found, please contact us at one of the above email addresses and we will attempt to repair them. Unless otherwise noted, content of this library is licensed under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a> on 20 April 2019 in memory of my Father, Robert Embry Turner - I LOVE YOU DAD! Rest In Peace. Please note that the <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> domain was acquired by Robert \"The R.A.T.\" Allen Turner on December 24, 2018 from the prior owners, which happen to be his brother and nephew. As such, \"The R.A.T.\" is unable to answer any inquiries regarding any products or services of <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> prior to that date. \"The R.A.T.\" also acquired the rights to all products previously produced by <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> and its previous owners. Those products will all be released as open source, under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a>, as time and resources permit.</p><center>This footprint is based on the locking header footprints developed by SparkFun, however, this footprint was created from scratch for inclusion in this library.</center>")
    (fp_text reference A1 (at 0 0 270) (layer F.SilkS) hide)
    (fp_text value 1X03-STAGGERED-S (at 0 0 270) (layer F.SilkS) hide)
    (pad 3 thru_hole circle (at 2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 12 /GND) (solder_mask_margin 0.1016))
    (pad 2 thru_hole circle (at 0 0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 26 /A12) (solder_mask_margin 0.1016))
    (pad 1 thru_hole rect (at -2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 1 /VCC) (solder_mask_margin 0.1016))
  )
  (module 27C512E-TO-2532S:1X03-STAGGERED (layer Top) (tedit 0)
    (at 159.6771 101.1936 270)
    (descr "<center><b>Single In Line Package (SIP) Header</b><br>Row Spacing: 0.6 inch (15.24 mm/600 mil)<br>Number of Pins: (Grid): 3 (1 x 3)<br>Pitch: 0.100 inch (2.54mm)<br>Mounting Type: Through Hole<br>Copyright ©07 Jan 2013, by:<br>\nRobert \"The R.A.T.\" Allen Turner<br>\n<a href=\"http://www.TheLittleEngineers.org/\">http://www.TheLittleEngineers.org/</a><br><a href=\"mailto:TheLittleEngineers@outlook.com\">TheLittleEngineers@outlook.com</a><br><a href=\"mailto:OurLittleEngineers@gMail.com\">OurLittleEngineers@gMail.com</a><br></center>\n<p align=\"justify\">You may use these footprints in your own projects, however, please take note that we CANNOT guarantee the accuracy of these components (nor any part of this library). We make NO guarantees that the components, footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for informational purposes only, and are used at your own discretion. By downloading these libraries, you agree that we cannot be held responsible for faulty PCBs. You should always check the footprints with a 1:1 printout. Neither Robert Allen Turner, <a href=\"http://www.TheLittleEngineers.org/\">The Little Engineers</a>, <a href=\"http://www.TheLittleEngineers.org/\">TheLittleEngineers.org,</a> <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a>, nor anyone affiliated with same shall be held responsible for any outcome resulting from the usage of these files. Should any errors be found, please contact us at one of the above email addresses and we will attempt to repair them. Unless otherwise noted, content of this library is licensed under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a> on 20 April 2019 in memory of my Father, Robert Embry Turner - I LOVE YOU DAD! Rest In Peace. Please note that the <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> domain was acquired by Robert \"The R.A.T.\" Allen Turner on December 24, 2018 from the prior owners, which happen to be his brother and nephew. As such, \"The R.A.T.\" is unable to answer any inquiries regarding any products or services of <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> prior to that date. \"The R.A.T.\" also acquired the rights to all products previously produced by <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> and its previous owners. Those products will all be released as open source, under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a>, as time and resources permit.</p><center>This footprint is based on the locking header footprints developed by SparkFun, however, this footprint was created from scratch for inclusion in this library.</center>")
    (fp_text reference A2 (at 0 0 270) (layer F.SilkS) hide)
    (fp_text value 1X03-STAGGERED-S (at 0 0 270) (layer F.SilkS) hide)
    (pad 3 thru_hole circle (at 2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 12 /GND) (solder_mask_margin 0.1016))
    (pad 2 thru_hole circle (at 0 0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 25 /A13) (solder_mask_margin 0.1016))
    (pad 1 thru_hole rect (at -2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 1 /VCC) (solder_mask_margin 0.1016))
  )
  (module 27C512E-TO-2532S:1X03-STAGGERED (layer Top) (tedit 0)
    (at 157.1371 101.1936 270)
    (descr "<center><b>Single In Line Package (SIP) Header</b><br>Row Spacing: 0.6 inch (15.24 mm/600 mil)<br>Number of Pins: (Grid): 3 (1 x 3)<br>Pitch: 0.100 inch (2.54mm)<br>Mounting Type: Through Hole<br>Copyright ©07 Jan 2013, by:<br>\nRobert \"The R.A.T.\" Allen Turner<br>\n<a href=\"http://www.TheLittleEngineers.org/\">http://www.TheLittleEngineers.org/</a><br><a href=\"mailto:TheLittleEngineers@outlook.com\">TheLittleEngineers@outlook.com</a><br><a href=\"mailto:OurLittleEngineers@gMail.com\">OurLittleEngineers@gMail.com</a><br></center>\n<p align=\"justify\">You may use these footprints in your own projects, however, please take note that we CANNOT guarantee the accuracy of these components (nor any part of this library). We make NO guarantees that the components, footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for informational purposes only, and are used at your own discretion. By downloading these libraries, you agree that we cannot be held responsible for faulty PCBs. You should always check the footprints with a 1:1 printout. Neither Robert Allen Turner, <a href=\"http://www.TheLittleEngineers.org/\">The Little Engineers</a>, <a href=\"http://www.TheLittleEngineers.org/\">TheLittleEngineers.org,</a> <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a>, nor anyone affiliated with same shall be held responsible for any outcome resulting from the usage of these files. Should any errors be found, please contact us at one of the above email addresses and we will attempt to repair them. Unless otherwise noted, content of this library is licensed under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a> on 20 April 2019 in memory of my Father, Robert Embry Turner - I LOVE YOU DAD! Rest In Peace. Please note that the <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> domain was acquired by Robert \"The R.A.T.\" Allen Turner on December 24, 2018 from the prior owners, which happen to be his brother and nephew. As such, \"The R.A.T.\" is unable to answer any inquiries regarding any products or services of <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> prior to that date. \"The R.A.T.\" also acquired the rights to all products previously produced by <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> and its previous owners. Those products will all be released as open source, under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a>, as time and resources permit.</p><center>This footprint is based on the locking header footprints developed by SparkFun, however, this footprint was created from scratch for inclusion in this library.</center>")
    (fp_text reference A3 (at 0 0 270) (layer F.SilkS) hide)
    (fp_text value 1X03-STAGGERED-S (at 0 0 270) (layer F.SilkS) hide)
    (pad 3 thru_hole circle (at 2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 12 /GND) (solder_mask_margin 0.1016))
    (pad 2 thru_hole circle (at 0 0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 24 /A14) (solder_mask_margin 0.1016))
    (pad 1 thru_hole rect (at -2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 1 /VCC) (solder_mask_margin 0.1016))
  )
  (module 27C512E-TO-2532S:1X03-STAGGERED (layer Top) (tedit 0)
    (at 154.5971 101.1936 270)
    (descr "<center><b>Single In Line Package (SIP) Header</b><br>Row Spacing: 0.6 inch (15.24 mm/600 mil)<br>Number of Pins: (Grid): 3 (1 x 3)<br>Pitch: 0.100 inch (2.54mm)<br>Mounting Type: Through Hole<br>Copyright ©07 Jan 2013, by:<br>\nRobert \"The R.A.T.\" Allen Turner<br>\n<a href=\"http://www.TheLittleEngineers.org/\">http://www.TheLittleEngineers.org/</a><br><a href=\"mailto:TheLittleEngineers@outlook.com\">TheLittleEngineers@outlook.com</a><br><a href=\"mailto:OurLittleEngineers@gMail.com\">OurLittleEngineers@gMail.com</a><br></center>\n<p align=\"justify\">You may use these footprints in your own projects, however, please take note that we CANNOT guarantee the accuracy of these components (nor any part of this library). We make NO guarantees that the components, footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for informational purposes only, and are used at your own discretion. By downloading these libraries, you agree that we cannot be held responsible for faulty PCBs. You should always check the footprints with a 1:1 printout. Neither Robert Allen Turner, <a href=\"http://www.TheLittleEngineers.org/\">The Little Engineers</a>, <a href=\"http://www.TheLittleEngineers.org/\">TheLittleEngineers.org,</a> <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a>, nor anyone affiliated with same shall be held responsible for any outcome resulting from the usage of these files. Should any errors be found, please contact us at one of the above email addresses and we will attempt to repair them. Unless otherwise noted, content of this library is licensed under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a> on 20 April 2019 in memory of my Father, Robert Embry Turner - I LOVE YOU DAD! Rest In Peace. Please note that the <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> domain was acquired by Robert \"The R.A.T.\" Allen Turner on December 24, 2018 from the prior owners, which happen to be his brother and nephew. As such, \"The R.A.T.\" is unable to answer any inquiries regarding any products or services of <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> prior to that date. \"The R.A.T.\" also acquired the rights to all products previously produced by <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> and its previous owners. Those products will all be released as open source, under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a>, as time and resources permit.</p><center>This footprint is based on the locking header footprints developed by SparkFun, however, this footprint was created from scratch for inclusion in this library.</center>")
    (fp_text reference A4 (at 0 0 270) (layer F.SilkS) hide)
    (fp_text value 1X03-STAGGERED-S (at 0 0 270) (layer F.SilkS) hide)
    (pad 3 thru_hole circle (at 2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 12 /GND) (solder_mask_margin 0.1016))
    (pad 2 thru_hole circle (at 0 0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 27 /A15) (solder_mask_margin 0.1016))
    (pad 1 thru_hole rect (at -2.54 -0.127) (size 1.524 1.524) (drill 1.016) (layers *.Cu *.Mask)
      (net 1 /VCC) (solder_mask_margin 0.1016))
  )
  (module 27C512E-TO-2532S:OUTLINE (layer Top) (tedit 0)
    (at 148.5011 105.0036)
    (descr "<center><b>Board Outline for the TheLittleEngineers.org-27C512E-TO-2532S-V1R1.20.APRIL.2019 Project.<br>Copyright ©01 Jun 2019, by:<br>\nRobert \"The R.A.T.\" Allen Turner<br>\n<a href=\"http://www.TheLittleEngineers.org/\">http://www.TheLittleEngineers.org/</a><br><a href=\"mailto:TheLittleEngineers@outlook.com\">TheLittleEngineers@outlook.com</a><br><a href=\"mailto:OurLittleEngineers@gMail.com\">OurLittleEngineers@gMail.com</a><br></center>\n<p align=\"justify\">You may use these footprints in your own projects, however, please take note that we CANNOT guarantee the accuracy of these components (nor any part of this library). We make NO guarantees that the components, footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for informational purposes only, and are used at your own discretion. By downloading these libraries, you agree that we cannot be held responsible for faulty PCBs. You should always check the footprints with a 1:1 printout. Neither Robert Allen Turner, <a href=\"http://www.TheLittleEngineers.org/\">The Little Engineers</a>, <a href=\"http://www.TheLittleEngineers.org/\">TheLittleEngineers.org,</a> <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a>, nor anyone affiliated with same shall be held responsible for any outcome resulting from the usage of these files. Should any errors be found, please contact us at one of the above email addresses and we will attempt to repair them. Unless otherwise noted, content of this library is licensed under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a> on 20 April 2019 in memory of my Father, Robert Embry Turner - I LOVE YOU DAD! Rest In Peace. Please note that the <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> domain was acquired by Robert \"The R.A.T.\" Allen Turner on December 24, 2018 from the prior owners, which happen to be his brother and nephew. As such, \"The R.A.T.\" is unable to answer any inquiries regarding any products or services of <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> prior to that date. \"The R.A.T.\" also acquired the rights to all products previously produced by <a href=\"http://www.GIMEchip.com/\">GIMEchip.com</a> and its previous owners. Those products will all be released as open source, under a Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license <a href=\"https://creativecommons.org/licenses/by-sa/4.0/\">(https://creativecommons.org/licenses/by-sa/4.0/)</a>, as time and resources permit.</p>")
    (fp_text reference U$1 (at 0 0) (layer F.SilkS) hide)
    (fp_text value "" (at 0 0) (layer F.SilkS) hide)
    (fp_line (start 19.1566 -43.8658) (end 10.2362 -43.8658) (layer Edge.Cuts) (width 0.1))
    (fp_arc (start 8.9662 -43.8658) (end 10.2362 -43.8658) (angle 180) (layer Edge.Cuts) (width 0.1))
    (fp_line (start 7.6962 -43.8658) (end -1.397 -43.8658) (layer Edge.Cuts) (width 0.1))
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  (gr_text D (at 154.0891 97.1296) (layer Top))
  (gr_text C (at 156.6291 97.1296) (layer Top))
  (gr_text B (at 159.1691 97.1296) (layer Top))
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  (gr_text D (at 154.0891 97.1296) (layer F.SilkS))
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  (gr_text B (at 159.1691 97.1296) (layer F.SilkS))
  (gr_text A (at 161.7091 97.1296) (layer F.SilkS))
  (gr_text TheLittleEngineers.org: (at 154.0891 94.5896 90) (layer F.SilkS))
  (gr_text 27C512E-TO-2532S-V1R1.20.APRIL.2019 (at 155.8671 94.3356 90) (layer F.SilkS))
  (gr_text "27C512 E.P.R.O.M. TO TMS2532 SOCKET" (at 157.3911 94.3356 90) (layer F.SilkS))
  (gr_text "CONVERTER. (C) 20 April 2019 and" (at 158.9151 94.3356 90) (layer F.SilkS))
  (gr_text "01 June 2019 by: Robert Allen Turner" (at 160.4391 94.3356 90) (layer F.SilkS))
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  (gr_text https://github.com/TheLittleEngineers (at 161.7091 96.1136 -90) (layer B.SilkS))
  (gr_text "Released under a Creative Commons" (at 160.1851 96.1136 -90) (layer B.SilkS))
  (gr_text "Attribution-ShareAlike 4.0 International" (at 158.6611 96.1136 -90) (layer B.SilkS))
  (gr_text "(CC BY-SA 4.0) License, 01 June 2019" (at 157.1371 96.1136 -90) (layer B.SilkS))
  (gr_text "In Memory of my Father, Robert Embry" (at 155.8671 96.1136 -90) (layer B.SilkS))
  (gr_text "Turner, 1945 - 2019. Rest In Peace." (at 154.3431 96.1136 -90) (layer B.SilkS))
  (gr_text "I LOVE YOU DAD!" (at 152.8191 96.1136 -90) (layer B.SilkS))
  (gr_text Ax (at 150.0251 101.9556) (layer Top))
  (gr_text High (at 147.4851 99.1616) (layer Top))
  (gr_text Low (at 148.5011 104.4956) (layer Top))
  (gr_text Ax (at 163.7411 101.9556) (layer Top))
  (gr_text 1 (at 164.5031 99.4156) (layer Top))
  (gr_text 0 (at 164.5031 104.2416) (layer Top))
  (gr_text High (at 147.4851 99.1616) (layer F.SilkS))
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  (gr_text 0 (at 164.5031 104.2416) (layer F.SilkS))
  (zone (net 12) (net_name /GND) (layer Top) (hatch edge 0.508)
    (priority 6)
    (connect_pads (clearance 0.000001))
    (min_thickness 0.254)
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  (zone (net 12) (net_name /GND) (layer Bottom) (hatch edge 0.508)
    (priority 6)
    (connect_pads (clearance 0.000001))
    (min_thickness 0.254)
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)
