(kicad_pcb (version 4) (host pcbnew 4.0.6)
  (general
    (links 10)
    (no_connects 0)
    (area 137.592999 103.556999 160.857001 118.947001)
    (thickness 1.6)
    (drawings 11)
    (tracks 43)
    (zones 0)
    (modules 5)
    (nets 9)
  )
  (page USLetter)
  (title_block
    (title "ATECC508A CryptoAuth Breakout Board")
    (date 2017-03-27)
    (rev 1.0)
    (company "CID Corporation")
    (comment 1 "Breakout from SOIC-8 Chip")
    (comment 2 "2 Flavors - I2C & 1Wire")
  )
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (user_trace_width 0.2032)
    (user_trace_width 0.254)
    (user_trace_width 0.3048)
    (user_trace_width 0.6096)
    (user_trace_width 0.8128)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFEF7F)
    (pcbplotparams
      (layerselection 0x010e0_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory Gerbers/))
  )
  (net 0 "")
  (net 1 /GND)
  (net 2 /VCC)
  (net 3 /SDA)
  (net 4 /SCL)
  (net 5 "Net-(U1-Pad1)")
  (net 6 "Net-(U1-Pad2)")
  (net 7 "Net-(U1-Pad3)")
  (net 8 "Net-(U1-Pad7)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net /GND)
    (add_net /SCL)
    (add_net /SDA)
    (add_net /VCC)
    (add_net "Net-(U1-Pad1)")
    (add_net "Net-(U1-Pad2)")
    (add_net "Net-(U1-Pad3)")
    (add_net "Net-(U1-Pad7)")
  )
  (module Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm (layer F.Cu) (tedit 58D99A8C)
    (at 154.94 110.9472 270)
    (descr "8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
    (tags "SOIC 1.27")
    (attr smd)
    (fp_text reference U1 (at -0.0508 0.1016 270) (layer F.SilkS))
    (fp_text value ATECC508A (at 0 3.5 270) (layer F.Fab) hide)
    (pad 1 smd rect (at -2.7 -1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 5 "Net-(U1-Pad1)"))
    (pad 2 smd rect (at -2.7 -0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 6 "Net-(U1-Pad2)"))
    (pad 3 smd rect (at -2.7 0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 7 "Net-(U1-Pad3)"))
    (pad 4 smd rect (at -2.7 1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 1 /GND))
    (pad 5 smd rect (at 2.7 1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 3 /SDA))
    (pad 6 smd rect (at 2.7 0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 4 /SCL))
    (pad 7 smd rect (at 2.7 -0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 8 "Net-(U1-Pad7)"))
    (pad 8 smd rect (at 2.7 -1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
      (net 2 /VCC))
    (model Housings_SOIC.3dshapes/SOIC-8_3.9x4.9mm_Pitch1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 58D999E6)
    (at 158.877 109.1692 270)
    (descr "Capacitor SMD 0603, hand soldering")
    (tags "capacitor 0603")
    (attr smd)
    (fp_text reference C1 (at 3.1496 -0.0762 270) (layer F.SilkS))
    (fp_text value 100nF (at -4.6228 0.0508 270) (layer F.Fab) hide)
    (pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 1 /GND))
    (pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 2 /VCC))
    (model ${KISYS3DMOD}/Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm (layer F.Cu) (tedit 58F672D5)
    (at 140.4112 107.6198)
    (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x04 2.54mm single row")
    (fp_text reference J1 (at 0 -2.39) (layer F.SilkS))
    (fp_text value CONN_01X04_MALE (at 0 10.01) (layer F.Fab) hide)
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 /GND))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 /SDA))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 /SCL))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 /VCC))
    (model Pin_Headers.3dshapes/Pin_Header_Straight_1x04_Pitch2.54mm.wrl
      (at (xyz 0 -0.15 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 90))
    )
  )
  (module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58F674D3)
    (at 150.4696 110.6424 270)
    (descr "Resistor SMD 0603, hand soldering")
    (tags "resistor 0603")
    (attr smd)
    (fp_text reference R1 (at -1.0922 1.4224 270) (layer F.SilkS))
    (fp_text value 4K7 (at 0 1.55 270) (layer F.Fab) hide)
    (fp_text user %R (at 0 0 270) (layer F.Fab))
    (pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
      (net 2 /VCC))
    (pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
      (net 3 /SDA))
    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58F674D7)
    (at 148.5392 114.173 90)
    (descr "Resistor SMD 0603, hand soldering")
    (tags "resistor 0603")
    (attr smd)
    (fp_text reference R2 (at -0.9652 1.4986 90) (layer F.SilkS))
    (fp_text value 4K7 (at 0 1.55 90) (layer F.Fab) hide)
    (fp_text user %R (at 0 0 90) (layer F.Fab))
    (pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
      (net 2 /VCC))
    (pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
      (net 4 /SCL))
    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_line (start 160.782 103.632) (end 137.668 103.632) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 160.782 118.872) (end 160.782 103.632) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 159.766 118.872) (end 160.782 118.872) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 158.75 118.872) (end 159.766 118.872) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 137.668 118.872) (end 158.75 118.872) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 137.668 103.632) (end 137.668 118.872) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_text ATECC508A (at 153.9748 105.2322) (layer F.SilkS))
  (gr_text GND (at 144.399 107.6706) (layer F.SilkS))
  (gr_text VCC (at 144.399 115.2144) (layer F.SilkS))
  (gr_text SCL (at 144.399 112.6744) (layer F.SilkS))
  (gr_text SDA (at 144.399 110.1598) (layer F.SilkS))
  (zone (net 1) (net_name /GND) (layer B.Cu) (hatch edge 0.508)
    (connect_pads (clearance 0.508))
    (min_thickness 0.254)
    (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
    (polygon
      (pts
        (xy 160.274 118.364) (xy 138.176 118.364) (xy 138.176 104.14) (xy 160.274 104.14)
      )
    )
  )
)
