(kicad_pcb (version 20171130) (host pcbnew 5.0.2+dfsg1-1)
  (general
    (thickness 1.6)
    (drawings 11)
    (tracks 31)
    (zones 0)
    (modules 2)
    (nets 7)
  )
  (page USLetter)
  (title_block
    (title "Project Title")
  )
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (34 B.Paste user hide)
    (35 F.Paste user hide)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user hide)
    (39 F.Mask user hide)
    (40 Dwgs.User user hide)
    (44 Edge.Cuts user)
    (46 B.CrtYd user hide)
    (47 F.CrtYd user hide)
    (48 B.Fab user hide)
    (49 F.Fab user hide)
  )
  (setup
    (last_trace_width 0.508)
    (user_trace_width 0.1524)
    (user_trace_width 0.381)
    (user_trace_width 0.508)
    (user_trace_width 0.635)
    (user_trace_width 0.762)
    (user_trace_width 1.27)
    (user_trace_width 2.032)
    (trace_clearance 0.254)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.1524)
    (segment_width 0.1524)
    (edge_width 0.1524)
    (via_size 0.6858)
    (via_drill 0.3302)
    (via_min_size 0.6858)
    (via_min_drill 0.3302)
    (user_via 0.6858 0.3302)
    (user_via 0.762 0.381)
    (user_via 1.016 0.508)
    (user_via 1.27 0.635)
    (uvia_size 0.6858)
    (uvia_drill 0.3302)
    (uvias_allowed no)
    (uvia_min_size 0)
    (uvia_min_drill 0)
    (pcb_text_width 0.1524)
    (pcb_text_size 1.016 1.016)
    (mod_edge_width 0.1524)
    (mod_text_size 1.016 1.016)
    (mod_text_width 0.1524)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.0508)
    (solder_mask_min_width 0.1016)
    (pad_to_paste_clearance -0.0508)
    (aux_axis_origin 0 0)
    (visible_elements FFFEDF7D)
    (pcbplotparams
      (layerselection 0x310fc_80000001)
      (usegerberextensions true)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "gerbers"))
  )
  (net 0 "")
  (net 1 /MISO)
  (net 2 /3V3)
  (net 3 /SCL)
  (net 4 /MOSI)
  (net 5 /CS_RST)
  (net 6 /GND)
  (net_class Default "This is the default net class."
    (clearance 0.254)
    (trace_width 0.254)
    (via_dia 0.6858)
    (via_drill 0.3302)
    (uvia_dia 0.6858)
    (uvia_drill 0.3302)
    (add_net /3V3)
    (add_net /CS_RST)
    (add_net /GND)
    (add_net /MISO)
    (add_net /MOSI)
    (add_net /SCL)
  )
  (module Connector_PinHeader_2.54mm:PinHeader_2x03_P2.54mm_Vertical (layer F.Cu) (tedit 5FB56FD6)
    (at 122.555 80.645)
    (descr "Through hole straight pin header, 2x03, 2.54mm pitch, double rows")
    (tags "Through hole pin header THT 2x03 2.54mm double row")
    (fp_text reference J1 (at 1.27 -2.33) (layer F.SilkS) hide)
    (fp_text value Conn_02x03_Odd_Even (at 1.27 7.41) (layer F.Fab))
    (fp_text user %R (at 1.27 2.54 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 /MISO))
    (pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 /3V3))
    (pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 /SCL))
    (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 /MOSI))
    (pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 /CS_RST))
    (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 /GND))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x03_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Connector_PinHeader_2.54mm:PinHeader_2x04_P2.54mm_Vertical (layer F.Cu) (tedit 5FB56FD1)
    (at 130.095001 79.295001)
    (descr "Through hole straight pin header, 2x04, 2.54mm pitch, double rows")
    (tags "Through hole pin header THT 2x04 2.54mm double row")
    (fp_text reference J2 (at 1.27 -2.33) (layer F.SilkS) hide)
    (fp_text value Conn_02x03_Odd_Even (at 1.27 9.95) (layer F.Fab))
    (fp_text user %R (at 1.27 3.81 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 5 /CS_RST))
    (pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 /3V3))
    (pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
    (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 /SCL))
    (pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
    (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 /MISO))
    (pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 6 /GND))
    (pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 /MOSI))
    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x04_P2.54mm_Vertical.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_arc (start 133.985 78.105) (end 134.62 78.105) (angle -90) (layer Edge.Cuts) (width 0.1524))
  (gr_arc (start 133.985 88.265) (end 133.985 88.9) (angle -90) (layer Edge.Cuts) (width 0.1524))
  (gr_arc (start 121.285 88.265) (end 120.65 88.265) (angle -90) (layer Edge.Cuts) (width 0.1524))
  (gr_arc (start 121.285 78.105) (end 121.285 77.47) (angle -90) (layer Edge.Cuts) (width 0.1524))
  (gr_line (start 120.65 78.105) (end 120.65 88.265) (layer Edge.Cuts) (width 0.1524))
  (gr_line (start 133.985 88.9) (end 121.285 88.9) (layer Edge.Cuts) (width 0.1524))
  (gr_line (start 134.62 78.105) (end 134.62 88.265) (layer Edge.Cuts) (width 0.1524))
  (gr_line (start 121.285 77.47) (end 133.985 77.47) (layer Edge.Cuts) (width 0.1524))
  (gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. BOARDS SHALL BE ROHS COMPLIANT. \n5. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n   SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n   WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n   MINIMUM SPACE - 0.006 INCH.\n   MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 16.51 171.45) (layer Dwgs.User))
)
