Altium

Design Rule Verification Report

Date: 12/26/2015
Time: 8:29:53 PM
Elapsed Time: 00:00:00
Filename: PCB1.CMPcbDoc
Errors: 0
Warnings: 0
Rule Violations: 0

Summary

Errors Count
0

Warnings Count
0

Rule Violations Count
Unpoured Polygon (Allow unpoured: False) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Width Constraint (Min=10mil) (Max=20mil) (Preferred=15mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=10mil) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total
0