(kicad_pcb (version 4) (host pcbnew 4.0.7-e2-6376~60~ubuntu17.10.1)
  (general
    (links 4)
    (no_connects 0)
    (area 139.785 93.857143 156.875 115.742857)
    (thickness 1.6)
    (drawings 6)
    (tracks 8)
    (zones 0)
    (modules 2)
    (nets 5)
  )
  (page A4)
  (title_block
    (title "FPC to DIP Breadboard adapter")
    (date 2018-04-13)
    (rev 0.1)
    (company "GDG Zürich")
  )
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.1)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.5 1.5)
    (pad_drill 0.6)
    (pad_to_mask_clearance 0)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory production/))
  )
  (net 0 "")
  (net 1 "Net-(J1-Pad1)")
  (net 2 "Net-(J1-Pad2)")
  (net 3 "Net-(J1-Pad3)")
  (net 4 "Net-(J1-Pad4)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(J1-Pad1)")
    (add_net "Net-(J1-Pad2)")
    (add_net "Net-(J1-Pad3)")
    (add_net "Net-(J1-Pad4)")
  )
  (module Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm (layer F.Cu) (tedit 5AD12D6B)
    (at 152.5 101.2)
    (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
    (tags "Through hole pin header THT 1x04 2.54mm single row")
    (fp_text reference J1 (at -2.4 0 90) (layer F.SilkS))
    (fp_text value Breadboard (at 3.3 3.5 90) (layer F.Fab))
    (fp_text user %R (at 0 3.81 90) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 1 "Net-(J1-Pad1)"))
    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 2 "Net-(J1-Pad2)"))
    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 3 "Net-(J1-Pad3)"))
    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
      (net 4 "Net-(J1-Pad4)"))
    (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x04_Pitch2.54mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module footprints:FPC_4_1mm (layer F.Cu) (tedit 5AD12D6F)
    (at 148.5011 105.0036 270)
    (fp_text reference J2 (at 0 2.2 270) (layer F.SilkS))
    (fp_text value "4 Pin FPC (1mm pitch)" (at -0.2036 7.6011 270) (layer F.Fab))
    (pad 1 smd rect (at -1.5 0 270) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask)
      (net 1 "Net-(J1-Pad1)"))
    (pad 2 smd rect (at -0.5 0 270) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(J1-Pad2)"))
    (pad 3 smd rect (at 0.5 0 270) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(J1-Pad3)"))
    (pad 4 smd rect (at 1.5 0 270) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask)
      (net 4 "Net-(J1-Pad4)"))
    (pad 0 smd rect (at -3.5 3 270) (size 2 1) (layers F.Cu F.Paste F.Mask))
    (pad 0 smd rect (at 3.5 3 270) (size 2 1) (layers F.Cu F.Paste F.Mask))
  )
  (gr_text www.rac.su (at 150.2 105.1 90) (layer B.SilkS))
  (gr_text "FPC Adapter\n1mm Pitch\nRev. 0.1" (at 145.9 105.1 90) (layer B.SilkS))
  (gr_line (start 142.5 111) (end 142.5 99) (angle 90) (layer Edge.Cuts) (width 0.1))
  (gr_line (start 154.7 111) (end 142.5 111) (angle 90) (layer Edge.Cuts) (width 0.1))
  (gr_line (start 154.7 99) (end 154.7 111) (angle 90) (layer Edge.Cuts) (width 0.1))
  (gr_line (start 142.5 99) (end 154.7 99) (angle 90) (layer Edge.Cuts) (width 0.1))
)
