(kicad_pcb (version 4) (host pcbnew 4.0.7)
  (general
    (links 11)
    (no_connects 1)
    (area 133.224999 100.724999 141.375001 109.075001)
    (thickness 0.8)
    (drawings 14)
    (tracks 60)
    (zones 0)
    (modules 4)
    (nets 7)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.4)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.8)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.05)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 GND)
  (net 2 VBUS)
  (net 3 "Net-(J1-Pad2)")
  (net 4 "Net-(J1-Pad3)")
  (net 5 /D+)
  (net 6 "Net-(J2-Pad3)")
  (net_class Default "This is the default net class."
    (clearance 0.2)
    (trace_width 0.4)
    (via_dia 0.8)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net /D+)
    (add_net GND)
    (add_net "Net-(J1-Pad2)")
    (add_net "Net-(J1-Pad3)")
    (add_net "Net-(J2-Pad3)")
    (add_net VBUS)
  )
  (module USB_5pin (layer F.Cu) (tedit 59B136DD)
    (at 137.31 108.97)
    (fp_text reference J1 (at 0 0.9) (layer F.SilkS) hide)
    (fp_text value USB_A (at -0.1 2.6) (layer F.Fab) hide)
    (fp_text user "PCB EDGE" (at 0 -0.3) (layer F.SilkS) hide)
    (pad 5 smd rect (at 1.3 -4.5) (size 0.4 2.1) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 4 smd rect (at 0.65 -4.5) (size 0.4 2.1) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 1 smd rect (at -1.3 -4.5) (size 0.4 2.1) (layers F.Cu F.Paste F.Mask)
      (net 2 VBUS))
    (pad 2 smd rect (at -0.65 -4.5) (size 0.4 2.1) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(J1-Pad2)"))
    (pad 5 smd rect (at 3.2 -3.7) (size 1.25 1) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad "" np_thru_hole circle (at 2 -3.55) (size 0.6 0.6) (drill 0.6) (layers *.Cu *.Mask))
    (pad 5 thru_hole circle (at 2.825 -1.45) (size 1.9 1.9) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad 5 thru_hole circle (at -2.825 -1.45) (size 1.9 1.9) (drill 1) (layers *.Cu *.Mask)
      (net 1 GND))
    (pad "" np_thru_hole circle (at -2 -3.55) (size 0.6 0.6) (drill 0.6) (layers *.Cu *.Mask))
    (pad 5 smd rect (at -3.2 -3.7) (size 1.25 1) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 3 smd rect (at 0 -4.5) (size 0.4 2.1) (layers F.Cu F.Paste F.Mask)
      (net 4 "Net-(J1-Pad3)"))
  )
  (module Resistors_SMD:R_0402_NoSilk (layer F.Cu) (tedit 59B132EC)
    (at 134.1 103.27 270)
    (descr "Resistor SMD 0402, reflow soldering, Vishay (see dcrcw.pdf)")
    (tags "resistor 0402")
    (attr smd)
    (fp_text reference R1 (at 0 -1.2 270) (layer F.SilkS) hide)
    (fp_text value 22R (at 0 1.25 270) (layer F.Fab) hide)
    (fp_text user %R (at 0 -1.2 270) (layer F.Fab) hide)
    (pad 1 smd rect (at -0.45 0 270) (size 0.4 0.6) (layers F.Cu F.Paste F.Mask)
      (net 5 /D+))
    (pad 2 smd rect (at 0.45 0 270) (size 0.4 0.6) (layers F.Cu F.Paste F.Mask)
      (net 4 "Net-(J1-Pad3)"))
    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0402.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Resistors_SMD:R_0402_NoSilk (layer F.Cu) (tedit 59B132F2)
    (at 140.49 103.2 270)
    (descr "Resistor SMD 0402, reflow soldering, Vishay (see dcrcw.pdf)")
    (tags "resistor 0402")
    (attr smd)
    (fp_text reference R2 (at 0 -1.2 270) (layer F.SilkS) hide)
    (fp_text value 22R (at 0 1.25 270) (layer F.Fab) hide)
    (fp_text user %R (at 0 -1.2 270) (layer F.Fab) hide)
    (pad 1 smd rect (at -0.45 0 270) (size 0.4 0.6) (layers F.Cu F.Paste F.Mask)
      (net 6 "Net-(J2-Pad3)"))
    (pad 2 smd rect (at 0.45 0 270) (size 0.4 0.6) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(J1-Pad2)"))
    (model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0402.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module KiCadCustomLibs:USB_PADS_Breakout (layer F.Cu) (tedit 5A3A0F42)
    (at 137.3 101.5)
    (fp_text reference J3 (at 0.3 1.6) (layer F.SilkS) hide)
    (fp_text value USB (at 0.1 -1.6) (layer F.Fab) hide)
    (pad 4 smd rect (at 2.25 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
      (net 1 GND))
    (pad 1 smd rect (at -2.25 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
      (net 2 VBUS))
    (pad 2 smd rect (at -0.75 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
      (net 5 /D+))
    (pad 3 smd rect (at 0.75 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
      (net 6 "Net-(J2-Pad3)"))
  )
  (gr_line (start 133.3 101.2) (end 133.3 109) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 141.3 101.2) (end 141.3 109) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 140.9 100.8) (end 133.7 100.8) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_arc (start 133.7 101.2) (end 133.3 101.2) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_arc (start 140.9 101.2) (end 140.9 100.8) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_text V (at 135.02 102.61 180) (layer F.SilkS))
  (gr_text - (at 138.05 102.57) (layer F.SilkS))
  (gr_text + (at 136.5 102.6) (layer F.SilkS))
  (gr_text G (at 139.57 102.61 180) (layer F.SilkS))
  (gr_text V (at 135.03 102.55 180) (layer B.SilkS))
  (gr_text - (at 138.05 102.38) (layer B.SilkS))
  (gr_text + (at 136.53 102.37) (layer B.SilkS))
  (gr_text G (at 139.52 102.53 180) (layer B.SilkS))
  (gr_line (start 133.3 109) (end 141.3 109) (angle 90) (layer Edge.Cuts) (width 0.15))
)
